Estimativas de Dark Silicon em projetos de sistemas Multicore

Detalhes bibliográficos
Ano de defesa: 2016
Autor(a) principal: Santos, Tony Carlos Bignardi dos
Orientador(a): Santos, Ricardo Ribeiro dos
Banca de defesa: Não Informado pela instituição
Tipo de documento: Dissertação
Tipo de acesso: Acesso aberto
Idioma: por
Instituição de defesa: Não Informado pela instituição
Programa de Pós-Graduação: Não Informado pela instituição
Departamento: Não Informado pela instituição
País: Não Informado pela instituição
Palavras-chave em Português:
Link de acesso: https://repositorio.ufms.br/handle/123456789/3001
Resumo: ABSTRACT - The demands for high-performance computing systems are still growing up significantly. Although the semiconductor industry is delivering efficient computing systems to the consumers, the physical and technological constraints can jeopardize the technological evolution to the next microprocessors generations. The static exponential power increase due to the leakage current in transistors below 90nm puts limits on the chip active area usage at runtime. The dark silicon concept refers to the amount of chip area working on reduced clock frequency to meet the thermal power constraints of the design. Among the alternatives to overpass the dark silicon are the adoption of parallel resources and hardware accelerators. Such alternatives enable the dark silicon areas to run in lower clock frequencies complying with the design power budget. Considering the lack of techniques and tools for the design of systems aware of dark silicon, this work focuses identifying and measuring the dark silicon on the chip on designs below 90nm using a methodology based on the power density of a base project (90nm) and a reference circuit. Experiments have been carried out on commercial multicore processors to estimate the dark silicon considering their technological advances. In addition, an experiment on design space exploration has been conducted to validate the dark silicon estimates and to look for alternatives to utilize the chip area on the physical constraints of project.