Estimativa e redução da dissipação de potência em redes intra-chip com chaveamento por pacotes

Detalhes bibliográficos
Ano de defesa: 2008
Autor(a) principal: Guindani, Guilherme Montez
Orientador(a): Moraes, Fernando Gehm
Banca de defesa: Não Informado pela instituição
Tipo de documento: Dissertação
Tipo de acesso: Acesso aberto
Idioma: por
Instituição de defesa: Pontifícia Universidade Católica do Rio Grande do Sul
Porto Alegre
Programa de Pós-Graduação: Não Informado pela instituição
Departamento: Não Informado pela instituição
País: Não Informado pela instituição
Palavras-chave em Português:
Link de acesso: http://hdl.handle.net/10923/1557
Resumo: The main cost functions in VLSI design during the 90’s were silicon area, performance, cost and reliability. Power dissipation and energy consumption were a secondary concern. For example, some Intel processors could dissipate more than 120 watts. Mobile computing changes this scenario, making energy consumption and battery life a primary concern. A first move to reduce power is to integrate most of the system functions together in a single integrated circuit, leading to the SoC concept. Due to number of functions integrated in modern SoCs, networks on chip (NoCs) are becoming the preferred communication infrastructure due to their scalability and communication parallelism. Current power estimation models for NoCs capitalize mostly in the volume of information transmitted through the network. This work proposes a more precise NoC power estimation model, based in the buffer reception rates, according to the traffic scenario applied to the network. Results show the accuracy of the model compared to industrial power estimation tools, with an error inferior to 10%, with reduced execution time. Compared to a volume based estimation method, it was possible to demonstrate the weakness of such methods, even if they are faster to generate results. The proposed model is integrated into the ATLAS framework, providing designers a path to evaluate power and energy of automatically generated NoCs. Additionally, this work evaluates the dissipation of each Hermes internal component, with and without power reduction techniques.