Implementação e avaliação de métodos para confiabilidade de redes intra-chip

• Ano de defesa: 2010
• Autor(a) principal: Silva, Alzemiro Henrique Lucas da
• Orientador(a): Moraes, Fernando Gehm
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Pontifícia Universidade Católica do Rio Grande do Sul; Porto Alegre
• Palavras-chave em Português: INFORMÁTICA; REDES DE COMPUTADORES; ARQUITETURA DE REDES; TOLERÂNCIA A FALHAS (INFORMÁTICA); CONFIABILIDADE DE SISTEMAS
• Link de acesso: http://hdl.handle.net/10923/1529

The innovations on integrated circuit fabrics are continuously reducing components size, which increases the logic density of systems‐on‐chip (SoC), but also affect the reliability of these components. Chip‐level global buses are especially subject to crosstalk faults, which can lead to increased delay and glitches. This work evaluates different fault tolerant approaches for Networkson‐ chip (NoCs) such that the network can maintain the original network performance even in the presence of faults. Four different approaches are presented and evaluated in terms of area overhead, packet latency, power consumption, and residual fault coverage. Results demonstrate that the use of CRC coding at each link is preferred when minimal area and power overhead are the main goals. However, each one of the methods presented here has its own advantages and can be applied depending on the target application.