Performance Comparison of Speculative Taskloop and OpenMP-for-Loop Thread-Level Speculation on Hardware Transactional Memory

• Main Author: Salamanca, Juan [UNESP]
• Publication Date: 2022
• Format: Conference object
• Language: eng
• Source: Repositório Institucional da UNESP
• Download full: http://dx.doi.org/10.1109/ISPDC55340.2022.00021; http://hdl.handle.net/11449/247961
• topic: Hardware Transactional Memory; OpenMP; parallel for; taskloop; Thread-Level Speculation

Speculative Taskloop (STL) is a loop parallelization technique that takes the best of Task-based Parallelism and Thread-Level Speculation to speed up loops with may loop-carried dependencies that were previously difficult for compilers to parallelize. Previous studies show the efficiency of STL when implemented using Hardware Transactional Memory and the advantages it offers compared to a typical DOACROSS technique such as OpenMP ordered. This paper presents a performance comparison between STL and a previously proposed technique that implements Thread-Level Speculation (TLS) in the for worksharing construct (FOR-TLS) over a set of loops from cbench and SPEC2006 benchmarks. The results show interesting insights on how each technique can be more appropriate depending on the characteristics of the evaluated loop. Experimental results reveal that by implementing both techniques on top of HTM, speed-ups of up to 2.41× can be obtained for STL and up to 2× for FOR-TLS.