Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP

Bibliographic Details
Main Author: Salamanca, Juan [UNESP]
Publication Date: 2022
Other Authors: Baldassin, Alexandro [UNESP]
Format: Conference object
Language: eng
Source: Repositório Institucional da UNESP
Download full: http://dx.doi.org/10.1007/978-3-031-15922-0_4
http://hdl.handle.net/11449/246141
Summary: This paper presents Speculative While (SWh), a technique that enables Speculative Task Execution (STE) in OpenMP to accelerate while loops marked by the proposed while construct and the swh clause. With SWh, the speculative tasks are generated by the OpenMP task construct in while loops (from linear algebra or goal finding algorithms) where control dependencies between iterations can be speculated. This paper also presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support to implement Speculative While and describes a preliminary evaluation of SWh implementation using HTM. As a result, it provides evidence to support the performance benefits of using STE over HTM to parallelize some well-known benchmarks. Experimental results reveal that by implementing SWh over HTM, speed-ups of up to 1.8 × can be obtained for the Gauss-Seidel benchmark.
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spelling Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMPOpenMPSpeculative WhileTransactional MemoryThis paper presents Speculative While (SWh), a technique that enables Speculative Task Execution (STE) in OpenMP to accelerate while loops marked by the proposed while construct and the swh clause. With SWh, the speculative tasks are generated by the OpenMP task construct in while loops (from linear algebra or goal finding algorithms) where control dependencies between iterations can be speculated. This paper also presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support to implement Speculative While and describes a preliminary evaluation of SWh implementation using HTM. As a result, it provides evidence to support the performance benefits of using STE over HTM to parallelize some well-known benchmarks. Experimental results reveal that by implementing SWh over HTM, speed-ups of up to 1.8 × can be obtained for the Gauss-Seidel benchmark.Sao Paulo State University (Unesp), SPSao Paulo State University (Unesp), SPUniversidade Estadual Paulista (UNESP)Salamanca, Juan [UNESP]Baldassin, Alexandro [UNESP]2023-07-29T12:32:49Z2023-07-29T12:32:49Z2022-01-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject50-64http://dx.doi.org/10.1007/978-3-031-15922-0_4Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), v. 13527 LNCS, p. 50-64.1611-33490302-9743http://hdl.handle.net/11449/24614110.1007/978-3-031-15922-0_42-s2.0-85140430318Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)info:eu-repo/semantics/openAccess2023-07-29T12:32:49Zoai:repositorio.unesp.br:11449/246141Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestrepositoriounesp@unesp.bropendoar:29462023-07-29T12:32:49Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false
dc.title.none.fl_str_mv Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP
title Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP
spellingShingle Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP
Salamanca, Juan [UNESP]
OpenMP
Speculative While
Transactional Memory
title_short Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP
title_full Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP
title_fullStr Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP
title_full_unstemmed Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP
title_sort Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP
author Salamanca, Juan [UNESP]
author_facet Salamanca, Juan [UNESP]
Baldassin, Alexandro [UNESP]
author_role author
author2 Baldassin, Alexandro [UNESP]
author2_role author
dc.contributor.none.fl_str_mv Universidade Estadual Paulista (UNESP)
dc.contributor.author.fl_str_mv Salamanca, Juan [UNESP]
Baldassin, Alexandro [UNESP]
dc.subject.por.fl_str_mv OpenMP
Speculative While
Transactional Memory
topic OpenMP
Speculative While
Transactional Memory
description This paper presents Speculative While (SWh), a technique that enables Speculative Task Execution (STE) in OpenMP to accelerate while loops marked by the proposed while construct and the swh clause. With SWh, the speculative tasks are generated by the OpenMP task construct in while loops (from linear algebra or goal finding algorithms) where control dependencies between iterations can be speculated. This paper also presents a detailed analysis of the application of Hardware Transactional Memory (HTM) support to implement Speculative While and describes a preliminary evaluation of SWh implementation using HTM. As a result, it provides evidence to support the performance benefits of using STE over HTM to parallelize some well-known benchmarks. Experimental results reveal that by implementing SWh over HTM, speed-ups of up to 1.8 × can be obtained for the Gauss-Seidel benchmark.
publishDate 2022
dc.date.none.fl_str_mv 2022-01-01
2023-07-29T12:32:49Z
2023-07-29T12:32:49Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/conferenceObject
format conferenceObject
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://dx.doi.org/10.1007/978-3-031-15922-0_4
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), v. 13527 LNCS, p. 50-64.
1611-3349
0302-9743
http://hdl.handle.net/11449/246141
10.1007/978-3-031-15922-0_4
2-s2.0-85140430318
url http://dx.doi.org/10.1007/978-3-031-15922-0_4
http://hdl.handle.net/11449/246141
identifier_str_mv Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), v. 13527 LNCS, p. 50-64.
1611-3349
0302-9743
10.1007/978-3-031-15922-0_4
2-s2.0-85140430318
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv 50-64
dc.source.none.fl_str_mv Scopus
reponame:Repositório Institucional da UNESP
instname:Universidade Estadual Paulista (UNESP)
instacron:UNESP
instname_str Universidade Estadual Paulista (UNESP)
instacron_str UNESP
institution UNESP
reponame_str Repositório Institucional da UNESP
collection Repositório Institucional da UNESP
repository.name.fl_str_mv Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)
repository.mail.fl_str_mv repositoriounesp@unesp.br
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