Conversor analógico digital de 10 bits utilizando arquitetura pipeline e tecnologia CMOS
| Ano de defesa: | 2015 |
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| Autor(a) principal: | |
| Orientador(a): | |
| Banca de defesa: | |
| Tipo de documento: | Dissertação |
| Tipo de acesso: | Acesso aberto |
| Idioma: | por |
| Instituição de defesa: |
Universidade Estadual Paulista (Unesp)
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| Programa de Pós-Graduação: |
Não Informado pela instituição
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| Departamento: |
Não Informado pela instituição
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| País: |
Não Informado pela instituição
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| Palavras-chave em Português: | |
| Link de acesso: | http://hdl.handle.net/11449/136044 http://www.athena.biblioteca.unesp.br/exlibris/bd/cathedra/03-03-2016/000859495.pdf |
Resumo: | In this work is presented a analog to digital converter with a resolution of 10 bits and pipeline architecture, which consists in a multi-converter competitive processing steps and the Nyquist Limit type. It is carried out the development of the parties of the converter with greater focus on the analog. Techniques for improving the performance of the converter are presented aiming primarily, minimization of the effects of the offset voltage comparators and low power consumption. An Operational Amplifier with positive feedback is presented aiming an increase of its gain, without compromising on your power consumption. The tests performed were made through simulations using CMOS technology 0.35 μm, voltage supply at 1.8 Volts and switching frequency of transistors of 5 MHz. These tests presented the results of the parties of the converter with the use of the techniques proposed, showing the reach of the expected results |