FANTNet: Uma Arquitetura para Rede de Trânsito NDN Baseada em Redes Definidas por Software

Detalhes bibliográficos
Ano de defesa: 2024
Autor(a) principal: Rosa, Eduardo Castilho
Orientador(a): Não Informado pela instituição
Banca de defesa: Não Informado pela instituição
Tipo de documento: Tese
Tipo de acesso: Acesso aberto
Idioma: por
Instituição de defesa: Universidade Federal de Uberlândia
Brasil
Programa de Pós-graduação em Ciência da Computação
Programa de Pós-Graduação: Não Informado pela instituição
Departamento: Não Informado pela instituição
País: Não Informado pela instituição
Palavras-chave em Português:
NDN
SDN
P4
FIB
Link de acesso: https://repositorio.ufu.br/handle/123456789/44322
http://doi.org/10.14393/ufu.te.2024.629
Resumo: The Named Data Networks (NDN) architecture was proposed to solve some of the limitations existing in the current Internet. Given the potential of NDN as an alternative to classic TCP/IP, routing traffic between multiple NDN domains over high-speed transit networks is critical. However, developing NDN packet forwarders for the core network brings numerous challenges, especially regarding the data structures for the NDN FIB on hardware. Although there are NDN FIB proposals for programmable switches, scaling them to store millions of prefixes in the ASIC is still a problem that needs to be satisfactorily resolved. Given this context, this thesis proposes FANTNet, a logically centralized NDN transit network architecture based on SDN. The FANTNet’s architecture aims to accelerate traffic between multiple NDN domains through an abstraction of the core network that uses programmable edge switches. To optimize forwarding in the core, we propose the Compressed Forwarding Information Base (CoFIB), a data structure for the FIB that is used exclusively in edge switches. CoFIB is implemented as a set of P4 tables arranged in the ingress and egress pipelines, where the algorithm proposed for LNPM uses multiple packet recirculations. We propose a heuristic for positioning the tables in the ingress and egress blocks to reduce the number of these recirculations. As a criterion for compressing prefixes in CoFIB, this thesis introduces the concept of canonical named prefixes and an algorithm for extracting these prefixes from the RIB. Experimental results show up to a 16.58× reduction in CoFIB on-chip memory consumption compared to the state-of-the-art, as well as a lower probability of lookup failures due to the low number of hash collisions. Furthermore, the results show a 23.17% increase in interest packets processed at line rate due to the table positioning optimization strategy.