Analysis and design of 7T sense amplifiers in 28 nm FD-SOI CMOS process

• Ano de defesa: 2019
• Autor(a) principal: Carvalho, Estêvão Fernandes de Lima
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: eng
• Instituição de defesa: Universidade Federal do Rio de Janeiro; Brasil; Instituto Alberto Luiz Coimbra de Pós-Graduação e Pesquisa de Engenharia; Programa de Pós-Graduação em Engenharia Elétrica; UFRJ
• Palavras-chave em Português: Atraso de tempo de trava; Otimização de trava; CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO
• Link de acesso: http://hdl.handle.net/11422/22720

The never ending strive to manufacture faster, smaller and energy efficient cir- cuits, made several nanometric effects (< 90 nm) sizable and unavoidable for circuit design, such as severe mismatch variations, limited supply voltage levels, high leak- age currents and several short-channel effects. Due to the low supply voltages used in these circuits, the classical strong inversion equations for bias currents and small- signal parameters turn out to be inaccurate, demanding more complexity to the model. On the other hand, state-of-art process such as FDSOI (Fully-Depleted Silicon on Insulator) can considerably reduce leakage currents and transistor mis- match while keeping speed and yield even with much lower energy consumption for operations centered around the moderate inversion region. This thesis focuses on the analysis of transistors operating in moderate inver- sion, by developing tools for designing the classical latch-type sense amplifier with 7 transistors (7T-LTSA) for sub/near-threshold operations in a 28 nm FDSOI CMOS process. Compact models for the latch time delay valid for any inversion level will be presented, which are valid for VDD=350 mV, 450 mV and 550 mV. Small-signal capacitances, transconductances and channel conductances are analyzed and mod- eled in order to provide compact and fast parameter evaluation. Lastly, a figure of merit (FoM) relating speed and yield is proposed. Energy consumption is minimized though the figure of merit at near-threshold supply voltage level. Time delay below 100 ps is reached with VDD=550 mV and below 1.5 ns with VDD=350 mV by proper transistor sizing of the 7T-LTSA, σof f is kept below 18 mV for a differential input voltage equals to 0.1VDD for VDD ranging from 350 mV to 550 mV.