Vericação funcional de sistemas digitais utilizando algoritmos genéticos na geração de dados aplicada a metodologia veriSC

• Ano de defesa: 2014
• Autor(a) principal: Franco, Ricardo Augusto Pereira
• Orientador(a): Silva, Karina Rocha Gomes da
• Banca de defesa: Silva, Karina Rocha Gomes da, Rodrigues, Cássio Leonardo, Cruz Júnior, Gélson da
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Goiás
• Programa de Pós-Graduação: Programa de Pós-graduação em Engenharia Elétrica e da Computação (EMC)
• Departamento: Escola de Engenharia Elétrica, Mecânica e de Computação - EMC (RG)
• País: Brasil
• Palavras-chave em Português: Vericação funcional; Metodologia VeriSC; Algoritmos genéticos; Cobertura funcional
• Palavras-chave em Inglês: Functional verication; VeriSC methodology; Genetic algorithms; Functional coverage
• Área do conhecimento CNPq: CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO
• Link de acesso: http://repositorio.bc.ufg.br/tede/handle/tede/5028

The process of creating an Intellectual Property Core (IP-core) has become more complex with the advent of electronic circuit technology, encouraging the development of new techniques and methodologies to assist this process. A fundamental and critical stage of a hardware design is the hardware verification phase. At this phase it is verified that the IP-core was implemented according to their specification, ensuring that it is feasible to prototyping and their large-scale production (System on Chip). The verification phase corresponds to the biggest bottleneck in a hardware design (BERGERON,2006). The VeriSC methodology is an implemented methodology to perform the hardware verifi- cation through simulation, that is, by means of functional verification. This work aims to complement the VeriSC methodology through the development of an algorithm based on the concept of Genetic Algorithms (GAs). The proposed algorithm will modify the data generation of this methodology, whose objective is to reduce the verification time and to improve the generated data by changing the data from pseudorandom mode to random-guided mode, increasing the reliability of the verification performed by the VeriSC methodology. The algorithm has a generic part (templates) that helps the implementation of new environment for the functional verification of new DUVs and it can be incorpo- rated into other functional verification methodologies. Finally, are presented three case studies, the stimuli created using GA are compared with the old implementation of VeriSC methodology.