Desemvolvimento de um simulador de um processador digital de sinais (DSP) utlizando a arquitetura multithread simultânea (SMT)

• Ano de defesa: 2003
• Autor(a) principal: Castanheira, Luís Gustavo
• Orientador(a): Saito, José Hiroki
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de São Carlos
• Programa de Pós-Graduação: Programa de Pós-Graduação em Ciência da Computação - PPGCC
• País: BR
• Palavras-chave em Português: Arquitetura de computador; Multuthread simultânea; Processador digital de sinais
• Área do conhecimento CNPq: CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO
• Link de acesso: https://repositorio.ufscar.br/handle/20.500.14289/305

Digital Signal Processors (DSPs) are used in a variety of applications such as telecommunications, audio equalization and video processing. These applications demand a huge numerical processing capacity and low development and production costs. The simultaneous multithreading (SMT) architecture´s goal is to increase processor performance through the better utilization of the functional units. In SMT several threads are executed simultaneously in the processor. SMT can be employed in DSPs, and it increases the performance of applications that can be parallelized, such as video processing algorithms. A filtering operation on an image, for example, can be divided into filtering operations on several subimages generated from the original image. A simulator was thus proposed to evaluate the performance of such architecture. To evaluate this performance, it will be used some signal and video processing routines as the one dimension fast Fourier transform (FFT) and an image spacial filtering operation, for example.