Implementação de um algoritmo de comunicação embarcado em dispositivo lógico programável com aplicação de técnica de multiplexação em frequência

• Main Author: Woss, Anderson Carlos
• Publication Date: 2014
• Format: Bachelor thesis
• Language: por
• Source: Repositório Institucional da UTFPR (da Universidade Tecnológica Federal do Paraná (RIUT))
• Download full: http://repositorio.utfpr.edu.br/jspui/handle/1/15819
• topic: Dispositivo de lógica programável; VHDL (Linguagem descritiva de hardware); Circuitos integrados - Simulação por computador; Arranjos de lógica programável em campo; Multiplexação; Rádio - Receptores e recepção; Programmable logic devices; VHDL (Computer hardware description language); Integrated circuits - Computer simulation; Field programmable gate arrays; Multiplexing; Radio - Receivers and reception; Engenharia Eletrônica

This paper describes the process of implementation in VHDL (VHSIC Hardware Description Language) of a communication algorithm with applications of OFDM (Orthogonal Frequency-Divide Multiplexing) technique and QAM (Quadrature Amplitude Modulation). The modulation can be done by Fourier transform or the fast Fourier transform (FFT) when digitally. Thus, the FFT is implemented based on the Cooley-Tukey algorithm, in the Radix-2 configuration, with a length of eight points, using numbers in floating-point representation of 32 bits. The code developed was synthesized in Altera Quartus II and simulated in ModelSim. As a result, it was possible to transmit a text of 561 characters successfully, from functional simulation, at a rate of 34.5 MB/s using a clock of 50 MHz, with possible recovery without errors at the receiver, however, due to the floating-point multiplications and structure adopted for the FFT, the synthesized code demanded more resources than available devices contained and was not possible embed it.