Digital system design process automation using place/transition petri nets
| Autor(a) principal: | |
|---|---|
| Data de Publicação: | 2009 |
| Outros Autores: | , |
| Tipo de documento: | Artigo de conferência |
| Idioma: | eng |
| Título da fonte: | Repositório Institucional da UNESP |
| Texto Completo: | http://dx.doi.org/10.3182/20091006-3-ES-4010.00017 http://hdl.handle.net/11449/71347 |
Resumo: | The constant increase in digital systems complexity definitely demands the automation of the corresponding synthesis process. This paper presents a computational environment designed to produce both software and hardware implementations of a system. The tool for code generation has been named ACG8051. As for the hardware synthesis there has been produced a larger environment consisting of four programs, namely: PIPE2TAB, AGPS, TABELA, and TAB2VHDL. ACG8051 and PIPE2TAB use place/transition net descriptions from PIPE as inputs. ACG8051 is aimed at generating assembly code for the 8051 micro-controller. PIPE2TAB produces a tabular version of a Mealy type finite state machine of the system, its output is fed into AGPS that is used for state allocation. The resulting digital system is then input to TABELA, which minimizes control functions and outputs of the digital system. Finally, the output generated by TABELA is fed to TAB2VHDL that produces a VHDL description of the system at the register transfer level. Thus, we present here a set of tools designed to take a high-level description of a digital system, represented by a place/transition net, and produces as output both an assembly code that can be immediately run on an 8051 micro-controller, and a VHDL description that can be used to directly implement the hardware parts either on an FPGA or as an ASIC. |
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Digital system design process automation using place/transition petri netsDesign automationDigital system synthesisFinite state machinePetri netAssembly codeCode GenerationComputational environmentsControl functionsDesign automationsDigital systemDigital system designHardware implementationsHardware synthesisHigh level descriptionPlace/transition Petri netsRegister transfer levelSynthesis processVHDL descriptionAutomationComputer aided designComputer hardware description languagesFinite automataHardwareMultiprocessing systemsPetri netsSystems analysisThe constant increase in digital systems complexity definitely demands the automation of the corresponding synthesis process. This paper presents a computational environment designed to produce both software and hardware implementations of a system. The tool for code generation has been named ACG8051. As for the hardware synthesis there has been produced a larger environment consisting of four programs, namely: PIPE2TAB, AGPS, TABELA, and TAB2VHDL. ACG8051 and PIPE2TAB use place/transition net descriptions from PIPE as inputs. ACG8051 is aimed at generating assembly code for the 8051 micro-controller. PIPE2TAB produces a tabular version of a Mealy type finite state machine of the system, its output is fed into AGPS that is used for state allocation. The resulting digital system is then input to TABELA, which minimizes control functions and outputs of the digital system. Finally, the output generated by TABELA is fed to TAB2VHDL that produces a VHDL description of the system at the register transfer level. Thus, we present here a set of tools designed to take a high-level description of a digital system, represented by a place/transition net, and produces as output both an assembly code that can be immediately run on an 8051 micro-controller, and a VHDL description that can be used to directly implement the hardware parts either on an FPGA or as an ASIC.Sao Paulo State University, Sao Jose do Rio Preto, SP 15054-000Sao Paulo State University, Ilha Solteira, SP 15385-000Sao Paulo State University, Sao Jose do Rio Preto, SP 15054-000Sao Paulo State University, Ilha Solteira, SP 15385-000Universidade Estadual Paulista (Unesp)Marranghello, Norian [UNESP]Da Silva, Alexandre C.R. [UNESP]Pereira, Aledir S. [UNESP]2014-05-27T11:24:05Z2014-05-27T11:24:05Z2009-12-01info:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject84-89http://dx.doi.org/10.3182/20091006-3-ES-4010.00017IFAC Proceedings Volumes (IFAC-PapersOnline), v. 4, n. PART 1, p. 84-89, 2009.1474-6670http://hdl.handle.net/11449/7134710.3182/20091006-3-ES-4010.000172-s2.0-7996093349720986232628927190000-0003-1086-3312Scopusreponame:Repositório Institucional da UNESPinstname:Universidade Estadual Paulista (UNESP)instacron:UNESPengIFAC Proceedings Volumes (IFAC-PapersOnline)info:eu-repo/semantics/openAccess2024-10-25T14:48:19Zoai:repositorio.unesp.br:11449/71347Repositório InstitucionalPUBhttp://repositorio.unesp.br/oai/requestrepositoriounesp@unesp.bropendoar:29462024-10-25T14:48:19Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP)false |
| dc.title.none.fl_str_mv |
Digital system design process automation using place/transition petri nets |
| title |
Digital system design process automation using place/transition petri nets |
| spellingShingle |
Digital system design process automation using place/transition petri nets Marranghello, Norian [UNESP] Design automation Digital system synthesis Finite state machine Petri net Assembly code Code Generation Computational environments Control functions Design automations Digital system Digital system design Hardware implementations Hardware synthesis High level description Place/transition Petri nets Register transfer level Synthesis process VHDL description Automation Computer aided design Computer hardware description languages Finite automata Hardware Multiprocessing systems Petri nets Systems analysis |
| title_short |
Digital system design process automation using place/transition petri nets |
| title_full |
Digital system design process automation using place/transition petri nets |
| title_fullStr |
Digital system design process automation using place/transition petri nets |
| title_full_unstemmed |
Digital system design process automation using place/transition petri nets |
| title_sort |
Digital system design process automation using place/transition petri nets |
| author |
Marranghello, Norian [UNESP] |
| author_facet |
Marranghello, Norian [UNESP] Da Silva, Alexandre C.R. [UNESP] Pereira, Aledir S. [UNESP] |
| author_role |
author |
| author2 |
Da Silva, Alexandre C.R. [UNESP] Pereira, Aledir S. [UNESP] |
| author2_role |
author author |
| dc.contributor.none.fl_str_mv |
Universidade Estadual Paulista (Unesp) |
| dc.contributor.author.fl_str_mv |
Marranghello, Norian [UNESP] Da Silva, Alexandre C.R. [UNESP] Pereira, Aledir S. [UNESP] |
| dc.subject.por.fl_str_mv |
Design automation Digital system synthesis Finite state machine Petri net Assembly code Code Generation Computational environments Control functions Design automations Digital system Digital system design Hardware implementations Hardware synthesis High level description Place/transition Petri nets Register transfer level Synthesis process VHDL description Automation Computer aided design Computer hardware description languages Finite automata Hardware Multiprocessing systems Petri nets Systems analysis |
| topic |
Design automation Digital system synthesis Finite state machine Petri net Assembly code Code Generation Computational environments Control functions Design automations Digital system Digital system design Hardware implementations Hardware synthesis High level description Place/transition Petri nets Register transfer level Synthesis process VHDL description Automation Computer aided design Computer hardware description languages Finite automata Hardware Multiprocessing systems Petri nets Systems analysis |
| description |
The constant increase in digital systems complexity definitely demands the automation of the corresponding synthesis process. This paper presents a computational environment designed to produce both software and hardware implementations of a system. The tool for code generation has been named ACG8051. As for the hardware synthesis there has been produced a larger environment consisting of four programs, namely: PIPE2TAB, AGPS, TABELA, and TAB2VHDL. ACG8051 and PIPE2TAB use place/transition net descriptions from PIPE as inputs. ACG8051 is aimed at generating assembly code for the 8051 micro-controller. PIPE2TAB produces a tabular version of a Mealy type finite state machine of the system, its output is fed into AGPS that is used for state allocation. The resulting digital system is then input to TABELA, which minimizes control functions and outputs of the digital system. Finally, the output generated by TABELA is fed to TAB2VHDL that produces a VHDL description of the system at the register transfer level. Thus, we present here a set of tools designed to take a high-level description of a digital system, represented by a place/transition net, and produces as output both an assembly code that can be immediately run on an 8051 micro-controller, and a VHDL description that can be used to directly implement the hardware parts either on an FPGA or as an ASIC. |
| publishDate |
2009 |
| dc.date.none.fl_str_mv |
2009-12-01 2014-05-27T11:24:05Z 2014-05-27T11:24:05Z |
| dc.type.status.fl_str_mv |
info:eu-repo/semantics/publishedVersion |
| dc.type.driver.fl_str_mv |
info:eu-repo/semantics/conferenceObject |
| format |
conferenceObject |
| status_str |
publishedVersion |
| dc.identifier.uri.fl_str_mv |
http://dx.doi.org/10.3182/20091006-3-ES-4010.00017 IFAC Proceedings Volumes (IFAC-PapersOnline), v. 4, n. PART 1, p. 84-89, 2009. 1474-6670 http://hdl.handle.net/11449/71347 10.3182/20091006-3-ES-4010.00017 2-s2.0-79960933497 2098623262892719 0000-0003-1086-3312 |
| url |
http://dx.doi.org/10.3182/20091006-3-ES-4010.00017 http://hdl.handle.net/11449/71347 |
| identifier_str_mv |
IFAC Proceedings Volumes (IFAC-PapersOnline), v. 4, n. PART 1, p. 84-89, 2009. 1474-6670 10.3182/20091006-3-ES-4010.00017 2-s2.0-79960933497 2098623262892719 0000-0003-1086-3312 |
| dc.language.iso.fl_str_mv |
eng |
| language |
eng |
| dc.relation.none.fl_str_mv |
IFAC Proceedings Volumes (IFAC-PapersOnline) |
| dc.rights.driver.fl_str_mv |
info:eu-repo/semantics/openAccess |
| eu_rights_str_mv |
openAccess |
| dc.format.none.fl_str_mv |
84-89 |
| dc.source.none.fl_str_mv |
Scopus reponame:Repositório Institucional da UNESP instname:Universidade Estadual Paulista (UNESP) instacron:UNESP |
| instname_str |
Universidade Estadual Paulista (UNESP) |
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UNESP |
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UNESP |
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Repositório Institucional da UNESP |
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Repositório Institucional da UNESP |
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Repositório Institucional da UNESP - Universidade Estadual Paulista (UNESP) |
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repositoriounesp@unesp.br |
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1834483450632994816 |