LTMS - Lups Transactional Memory Scheduler: um escalonador NUMA-Aware para STM

• Main Author: Costa, Michael Alexandre
• Publication Date: 2021
• Format: Master thesis
• Language: por
• Source: Repositório Institucional da UFPel - Guaiaca
• Download full: http://guaiaca.ufpel.edu.br/handle/prefix/8016
• topic: Computação; Memórias Transacionais - TM; Non-Uniform Memory Access - NUMA; Escalonador; Transactional Memory - TM; Non-Uniform Memory Access - NUMA; Scheduler; CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO

Software Transactional Memory (STM) is an alternative to synchronization using locks and monitors. STM allows the programmer to write parallel codes in a simpler way, as it is possible to replace the use of locks with atomic blocks. However, with the increase in parallelism, there is an increase in contention, which in STM is reflected in a greater number of conflicts. Seeking to optimize STM performance, many studies focus on reducing the number of conflicts through schedulers. However, in current architectures, it is also important to consider where program memory is allocated and how it is accessed. This dissertation proposes a NUMA-Aware scheduler for STM, entitled Lups Transactional Memory Scheduler (LTMS), which, at runtime, collects data about the application and architecture used to optimize the execution of STM in NUMA architectures. For this, the scheduling strategy is divided into three steps. The first provides an initialization mechanism, creating queues that reflect the thread distribution architecture and strategies, to analyze the impact that thread distribution has on the application. The second step presents a mechanism to collect data at runtime, in this step data about the threads and their transactions, memory accesses and the used architecture are collected. The third step brings a system for migration of threads at runtime, which comes into action after a conflict occurs, this step seeks to group conflicting threads minimizing future conflicts and reducing the cost of memory access. For decision-making at this stage, two heuristics were developed to understand the STM behavior in relation to latency cost and conflict intensity. To carry out tests, the LTMS was implemented with the TinySTM library and was used with a set of STAMP benchmarks. The experiments were performed using the different thread distribution and migration strategies developed and compared with the TinySTM 1.0.5 library. The experiments showed for most benchmarks lower abort rate and better execution time.