On generating VHDL descriptions from aspect-oriented UML/MARTE models

• Main Author: Wehrmeister M.A.
• Publication Date: 2014
• Other Authors: Leite M.*
• Format: Conference object
• Language: eng
• Source: Repositório Institucional da Udesc
• dARK ID: ark:/33523/0013000004z16
• Download full: https://repositorio.udesc.br/handle/UDESC/8457

© 2015 IEEE.This paper discusses an approach to generate VHDL descriptions from high-level specifications, specifically UML/MARTE models that include aspect-oriented semantics. Standard UML diagrams describe the handling of functional requirements, whereas crosscutting concerns associated with the non-functional requirements are handle by aspects. UML-to- VHDL transformation is performed automatically by a scriptbased code generation tool named GenERTiCA. For that, mapping rules scripts define how to generate VHDL constructs from model elements, including the implementation of aspects adaptations. The generated VHDL description does not require any manual modification, in order to be fully synthesized onto a FPGA device. Some case studies have been performed to evaluate the proposed approach, however, this paper discusses the linefollowing robot implemented as a FPGA-based embedded system. An improvement in system design has been obtained, namely an increase in system performance and a better utilization of FPGA reconfigurable resources. Such positive results are related to a better modularization of components achieved by using the proposed high-level approach.