Lightweight and Efficient Architecture for AES Algorithm based on FPGA

• Main Author: Abebe, Abiy Tadesse
• Publication Date: 2023
• Format: Article
• Language: eng
• Source: Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
• Download full: https://doi.org/10.34629/ipl.isel.i-ETC.96
• topic: AES, cryptography, FPGA based implementation, parallel pipelining

Different platforms, such as resource limited devices and high-performance processors, are used in IoT networks, each with its own set of resource, performance, and security needs. It is critical to optimize existing standard cryptographic algorithms to meet the needs of today's networks, yet this is a difficult undertaking. In this paper, a compact and efficient architecture for the Advanced Encryption Standard (AES) is developed and implemented using several FPGA platforms, with the goal of addressing both restricted and high-performance platforms in IoT networks. To create compact and efficient AES based on FPGA, a hybrid optimization technique is applied. The implementation makes advantage of FPGA embedded resources such as BRAMs and DSP slices. To synthesize and implement it on the Xilinx Virtex-7 device, the Vivado HLS tool 2019.1 is utilized. Similarly, as devices older than the Xilinx 7-series platforms are not directly supported by Vivado HLS tool, Xilinx 14.5 ISE tool is used to synthesize and implement it. Smaller resources, such as 572 slices, 8 BRAMs, and 32 DSP slices, are used in comparison to the implementation outcomes found in literature. Additionally, improved throughput performance (112.399 Gbps) was achieved by satisfying the current work's optimization targets.