Improved dependability for dynamically reconfigurable hardware: restoration of the reliability index via replication and error correction

• Main Author: José Martins Ferreira
• Publication Date: 2004
• Other Authors: Manuel G. Gericota
• Format: Book
• Language: eng
• Source: Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
• Download full: https://repositorio-aberto.up.pt/handle/10216/84067
• topic: Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática; Electrical engineering, Electrical engineering, Electronic engineering, Information engineering

Fault-tolerant (FT) architectures based on classic spatial and temporal redundancy are used in anincreasing number of applications. However, the hardware platforms underlying modern highreliabilitysystems have little resemblance to those that were common when such architectureswere devised. The earlier fault models are not necessarily out-of-date (e.g. stuck-at faults stillplay an important role for validating FT applications), but the new failure modes of nanometertechnologies were largely irrelevant when J. von Neumanns paper on the synthesis of reliableorganisms from unreliable components was published in the 1950s. Such concerns areparticularly relevant when designing high-reliability adaptive systems, where reconfigurablefield-programmable gate arrays (FPGAs) are increasingly used. On the other hand, theeconomics of FT architectures based on spatial redundancy (e.g. triple modular redundancy,TMR), are entirely different when evaluated under the assumption of such features as dynamicreconfiguration, which enables just-in-time implementation of only those resources that need tobe available at any given time, or self-reconfiguration, which enables self-contained correctiveactions that are able to isolate / replace defective resources. New design approaches are therefore required to cope with the challenges introduced by each new generation ofprogrammable hardware devices. This paper presents an approach to design high-reliabilityarchitectures at lower cost, by taking advantage of dynamic / self reconfiguration and built-intest infrastructures, which are present in modern generations of FPGAs.