Analog flat-level circuit synthesis with genetic algorithms

• Main Author: Gomes, Miguel
• Publication Date: 2024
• Other Authors: Tavares, Rui, Goes, João
• Format: Article
• Language: eng
• Source: Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
• Download full: http://hdl.handle.net/10400.21/17846
• topic: Automatic topology generation; Genetic algorithm; Electronic design automation; Variable length chromosome; Simulator-in-the-loop; Analog circuit synthesis; Ngspice

This paper proposes new techniques for automatic simulation-based analog circuit synthesis using genetic algorithms. This is intended to contribute to the set of electronic design automation tools that use genetic algorithms in circuit synthesis, especially those that use the simulator-in-the-loop paradigm. In this study, a genetic algorithm was employed as the generation engine for analog circuits, and variable-length chromosomes were used to describe circuit topology. The entire process is carried out on a flat level (device level), i.e. using the transistor and other elementary devices (e.g. resistors) as the basic elementary blocks. Circuit synthesis is accomplished without any knowledge of previously defined topologies (or analog block cells). Three techniques are presented for analog circuit synthesis that are incorporated in the genetic algorithm, which contribute to its robustness, leading to better and faster results. These techniques can be summarized as follows: 1) adaptive probability of chromosome acceptance, 2) removal of redundant or useless components, and 3) segmented evolution. The automatic process starts with the circuit input and output specifications and proceeds with the evolution of both circuit topology and component sizing. The results shown in this paper include a 40 dB DC gain amplifier, which, when evaluated with SPECTRE/CADENCE 6.0, using a standard 130 nm technology, with a load capacitor of 10 pF, has a gain of 102 V/V, a GBW product of 70 MHz, and a figure of merit of 1436 MHz.pF/mW.