5G O-RAN Fronthaul P4 Switch

• Main Author: Marques, Diogo Costa
• Publication Date: 2021
• Format: Master thesis
• Language: eng
• Source: Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
• Download full: http://hdl.handle.net/10773/33933
• topic: 5G; Open RAN; Fronthaul; P4; Switch; FPGA

The development of mobile communication networks has led to the creation of the fifth generation of cellular networks (5G) to meet new requirements and new use cases. 5G is expected to have a large impact not only on society but also in industry, enabling increased peak data rates, low latency and the connectivity needed to link everything, including machines and devices, enabling the next level of world connectivity. The 5G RAN has become a collection of base stations that support the capabilities of data transport, radio transmission and reception. By providing connectivity between devices and sensors with their core network, is the key element of a 5G system that needs to evolve to enable today’s requirements. Thus, the RAN has seen its architecture become more centralized and virtualized. Initially, C-RAN architecture proposed a division of the RAN in two, with a fixed function split and a fronthaul link that links both units. There was a need for more flexibility and a new RAN arises with the split into CU, DU and RU with various options in the functional split. The O-RAN intends to evolve the RAN to a network more software-driven, virtualized and flexible, supporting interoperation between vendors. Taking into consideration the requirements that a fronthaul link has, such as restricted time windows since it is dealing with radio signals, the goal of this dissertation is the design of a switch that allows the fronthaul link of an O-RAN to be shared by general-purpose traffic. The high performance three-port switch combines general-purpose and high-priority traffic in one optical link at both ends of the fronthaul link. The P4-SDNET tool was used to describe how the data plane processes the packets through the P4 language. The development is done by using a development kit based on FPGA and the Xilinx SDNet high-level environment that allows the design of packet-processing data plane with P4 languages that target FPGA hardware. A traffic generation platform was also designed, based on the same kit, to test the latency that the switches add to the fronthaul. Positive results were obtained with added latencies between 1 and 3 microseconds for O-RAN traffic. However, the main limitation of the system is the recognition of S-Plane traffic.