Using a hardware coprocessor for message scheduling in fieldbus-based distributed systems

• Main Author: Fonseca, José A.
• Publication Date: 2001
• Other Authors: Martins, Ernesto V., Neves, Paulo Alexandre
• Language: eng
• Source: Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
• Download full: http://hdl.handle.net/10400.11/527
• topic: Hardware co-processor; FPGA - Fiel Programmable Gate Arrays; Controller area network; Message scheduling in fieldbus systems; Fieldbus

Fieldbus based distributed embedded systems used in real-time applications tend to be inflexible in what concerns changing operational parameters on-line. Recent techniques such as the planning scheduler can avoid this problem but do not show adequate responsiveness f o r automatic negotiation of parameter values. In this paper the use of ASIC based coprocessors f o r message scheduling is proposed to solve the problem. Such coprocessors can be used in the arbiter nodes of systems based on widely used producer-consumer fieldbuses like WorldFIP and CAN. A prototype built with a Xilinx FPGA is presented. First performance results are shown and analyzed. They demonstrate that the device is able to achieve the expected performance and also point to the possibility of evolution to an almost dynamic scheduling approach.