A Memetic Algorithm for Logic Circuit Design
| Main Author: | |
|---|---|
| Publication Date: | 2005 |
| Other Authors: | , |
| Language: | eng |
| Source: | Repositórios Científicos de Acesso Aberto de Portugal (RCAAP) |
| Download full: | http://hdl.handle.net/10400.22/13234 |
Summary: | Memetic Algorithms (MAs) have shown to be very effective in solving many hard combinatorial optimization problems. In this perspective, this paper presents a MA for combinational logic circuits synthesis. The proposed MA combines a Genetic Algorithm (GA) for digital circuit design with the gate type local search (GTLS). The combination of a global and a local search is a strategy used by many successful hybrid optimization approaches. The main idea is to apply a local refinement to an Evolutionary Algorithm (EA) in order to improve the fitness of the individuals in the population. The obtained results indicate that the MA reduces the number of generations required to reach the solutions and its standard deviation while improves the final fitness function. |
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A Memetic Algorithm for Logic Circuit DesignArtificial intelligenceDigital circuitsEvolutionary computationGenetic algorithmsLogic designMemetic algorithmsMemetic Algorithms (MAs) have shown to be very effective in solving many hard combinatorial optimization problems. In this perspective, this paper presents a MA for combinational logic circuits synthesis. The proposed MA combines a Genetic Algorithm (GA) for digital circuit design with the gate type local search (GTLS). The combination of a global and a local search is a strategy used by many successful hybrid optimization approaches. The main idea is to apply a local refinement to an Evolutionary Algorithm (EA) in order to improve the fitness of the individuals in the population. The obtained results indicate that the MA reduces the number of generations required to reach the solutions and its standard deviation while improves the final fitness function.REPOSITÓRIO P.PORTOReis, CecíliaTenreiro Machado, J. A.Cunha, J. Boaventura2019-03-29T12:06:17Z2005-112005-11-01T00:00:00Zconference objectinfo:eu-repo/semantics/publishedVersionapplication/pdfhttp://hdl.handle.net/10400.22/13234enginfo:eu-repo/semantics/openAccessreponame:Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)instname:FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologiainstacron:RCAAP2025-04-02T03:31:54Zoai:recipp.ipp.pt:10400.22/13234Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireinfo@rcaap.ptopendoar:https://opendoar.ac.uk/repository/71602025-05-29T00:59:35.029594Repositórios Científicos de Acesso Aberto de Portugal (RCAAP) - FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologiafalse |
| dc.title.none.fl_str_mv |
A Memetic Algorithm for Logic Circuit Design |
| title |
A Memetic Algorithm for Logic Circuit Design |
| spellingShingle |
A Memetic Algorithm for Logic Circuit Design Reis, Cecília Artificial intelligence Digital circuits Evolutionary computation Genetic algorithms Logic design Memetic algorithms |
| title_short |
A Memetic Algorithm for Logic Circuit Design |
| title_full |
A Memetic Algorithm for Logic Circuit Design |
| title_fullStr |
A Memetic Algorithm for Logic Circuit Design |
| title_full_unstemmed |
A Memetic Algorithm for Logic Circuit Design |
| title_sort |
A Memetic Algorithm for Logic Circuit Design |
| author |
Reis, Cecília |
| author_facet |
Reis, Cecília Tenreiro Machado, J. A. Cunha, J. Boaventura |
| author_role |
author |
| author2 |
Tenreiro Machado, J. A. Cunha, J. Boaventura |
| author2_role |
author author |
| dc.contributor.none.fl_str_mv |
REPOSITÓRIO P.PORTO |
| dc.contributor.author.fl_str_mv |
Reis, Cecília Tenreiro Machado, J. A. Cunha, J. Boaventura |
| dc.subject.por.fl_str_mv |
Artificial intelligence Digital circuits Evolutionary computation Genetic algorithms Logic design Memetic algorithms |
| topic |
Artificial intelligence Digital circuits Evolutionary computation Genetic algorithms Logic design Memetic algorithms |
| description |
Memetic Algorithms (MAs) have shown to be very effective in solving many hard combinatorial optimization problems. In this perspective, this paper presents a MA for combinational logic circuits synthesis. The proposed MA combines a Genetic Algorithm (GA) for digital circuit design with the gate type local search (GTLS). The combination of a global and a local search is a strategy used by many successful hybrid optimization approaches. The main idea is to apply a local refinement to an Evolutionary Algorithm (EA) in order to improve the fitness of the individuals in the population. The obtained results indicate that the MA reduces the number of generations required to reach the solutions and its standard deviation while improves the final fitness function. |
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2005 |
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2005-11 2005-11-01T00:00:00Z 2019-03-29T12:06:17Z |
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conference object |
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http://hdl.handle.net/10400.22/13234 |
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http://hdl.handle.net/10400.22/13234 |
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eng |
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