Implementação de um sistema de transferência de dados de ultrassom via Ethernet e processamento embarcado em dispositivo FPGA
| Ano de defesa: | 2020 |
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| Autor(a) principal: | |
| Orientador(a): | |
| Banca de defesa: | |
| Tipo de documento: | Dissertação |
| Tipo de acesso: | Acesso aberto |
| Idioma: | por |
| Instituição de defesa: |
Universidade Tecnológica Federal do Paraná
Curitiba Brasil Programa de Pós-Graduação em Sistemas de Energia UTFPR |
| Programa de Pós-Graduação: |
Não Informado pela instituição
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| Departamento: |
Não Informado pela instituição
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| País: |
Não Informado pela instituição
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| Palavras-chave em Português: | |
| Link de acesso: | http://repositorio.utfpr.edu.br/jspui/handle/1/5100 |
Resumo: | The generation of ultrasound images to aid in the diagnosis, characterization and nondestructive evaluation of materials requires high power of digital signal processing and capacity for massive data transfer. In order to circumvent the typically closed architecture of most commercial ultrasound equipment, as well as optimize resources and improve the quality of the images generated by the technique, several research groups have presented new approaches to ultrasound imaging. At the Federal Technological University of Paraná, the Ultrasound Research Group has been working on development of the open research platform ULTRA-ORS (Ultrasound Open Research System) which, although is suitable for the requirements of flexibility and ultrasound dataflow, it exceeds the data transfer and processing time to generate images in real time. In this work, we propose the implementation of a system for transferring raw ultrasound signals with high speed processing for reconstruction of B Mode image in reconfigurable hardware architecture, aiming at a reduction at the time required for transfer and computation. The proposed system consists of two FPGA development boards: Terasic DE2- 115 and DE4-230 (Terasic Inc., Taiwan). The first board has the function of assembling and transmitting data packets via an Ethernet network using the TCP/IP communication protocol. The second board receives the packets and performs the processing for image reconstruction using the beamforming Delay and Sum (DAS) technique for 8 and 32 active aperture elements. In addition to the Quartus Prime software and the Qsys tool, the DSP Builder library was used in the Simulink environment for modeling, simulation and transformation of the following models in hardware description language (HDL): Finite Impulse Response (FIR) filter, variable delay, apodization, coherent summation, demodulation with envelope detection based on the Hilbert Transform approximation and logarithmic compression. For the algorithm implementation and evaluation, within two FPGA devices, raw ultrasound data were used, acquired by the ULTRA-ORS system with a sampling frequency of 40 MHz and 12-bits resolution, using a convex transducer of 128 elements in an ultrasound phantom. The experimental result of the processing was transferred to a computer for later scan conversion and display on monitor. For the quantitative and qualitative assessments of the accuracy of the presented method, the cost function of the square root of the normalized mean square error (NRMSE) was used in comparison with the same functions implemented through a script in Matlab, simulation in Simulink and reconstructed images. Finally, the contrast ratio (CR) and contrast-noise ratio (CNR) were applied to evaluate the generated images. All results showed excellent agreement with NRMSE below 10%. The CR and CNR errors were less than 5.7% and 6.8%, respectively. There has been a significant improvement in the maximum processing time, going from 30 minutes to 9 seconds. However, further studies are needed to enable the generation of ultrasound images in real-time. |