Design of a low-power 10-bit 12-MS/s asynchronous SAR ADC

• Ano de defesa: 2020
• Autor(a) principal: Campos, Arthur Lombardi
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: eng
• Instituição de defesa: Biblioteca Digitais de Teses e Dissertações da USP
• Palavras-chave em Português: Analog-to-Digital Converter; Asynchronous SAR ADC; Baixo consumo de energia; Circuitos Integrados; Conversor Analógico-Digital; Integrated Circuits; Internet das coisas; Internet of Things; Low power consumption; Receivers; Receptores; SAR ADC assíncrono
• Link de acesso: https://www.teses.usp.br/teses/disponiveis/18/18152/tde-16122021-162821/

This work presents the design of a low-power 10-bit 12-MS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in 65-nm technology, suitable for IEEE 802.15.4g standard frontend receivers (low data rate and power consumption smart utility networks). By using the differential implementation with a pair of bootstrapped switches, the input signal is sampled with low distortion. The asynchronous implemen-tation of the SAR circuit leads to an increased system flexibility because only a single clock source is required. To support the merged capacitor switching scheme (MCS), a three-level switch circuit was designed for the capacitor array. The simulated circuit achieved a 9.65 ENOB with 151.4 μW of power consumption at 12 MS/s, leading to a FOM of 15.8 fJ/Conversion-step. Simulations have also shown that the ADC is efficient for sampling frequencies ranging from 10 kS/s up to 12 MS/s, extending its usability to low sampling frequency circuits.