Multifractal traffic generator modeled at the transaction level for integrates systems performance evaluation.

• Ano de defesa: 2017
• Autor(a) principal: Bueno Filho, José Eduardo Chiarelli
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: eng
• Instituição de defesa: Biblioteca Digitais de Teses e Dissertações da USP
• Palavras-chave em Português: Fractais; Modelos em séries temporais; Multifractal model; On-chip traffic; Sistemas integrados em larga escala; Speedup-accuracy trade-off; Traffic generator; Transaction level modeling
• Link de acesso: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-28062017-114833/

The present work aims to provide a contribution to improve the efficiency the design flow of integrated systems, focusing, specifically, on the performance evaluation of its communication structures. The use of Transaction Level Modeling (TLM) is proposed, in order to take advantage of the reduction of design effort and time. Within the performance evaluation approaches, the utilization of traffic generators instead of full system simulations started to be adopted due to its higher time efficiency. Initial works on on-chip traffic generation focused on Poisson processes and classic Markovian models, which are unable to capture Long Range Dependence (LRD). This fact led to the adoption of fractal/self-similar models. Later advancements have shown that the traffic produced in multiprocessed systems can show higher degrees of complexity, what can be attributed to the presence multifractal characteristics. In this work, a methodology to evaluate the on-chip traffic and to the development of a transaction level traffic generator is proposed. The main contributions of this work are a detailed analysis of traffic time series obtained by TLM simulations and the study of the effects of the traffic generator on these simulations, concerning, mainly, the speedup-accuracy trade-off. The proposed analysis follow the multifractal paradigm, allowing system developers to (1) understand the statistical nature of on-chip traffic, (2) to obtain accurate representations of this traffic and (3) to build traffic generators that mimic processing elements realistically. Another contribution of this work is a comparison of the performance, considering the accuracy of the obtained synthetic traffic time series, between monofractal and multifractal models. All of the mentioned contributions were grouped throughout the detailed methodology presented on the present document, for which experiments were carried out.