Modelo unificado de padrões paralelos elásticos para implementação de aplicações
Ano de defesa: | 2023 |
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Autor(a) principal: | |
Orientador(a): | |
Banca de defesa: | , , , |
Tipo de documento: | Dissertação |
Tipo de acesso: | Acesso aberto |
Idioma: | por |
Instituição de defesa: |
Universidade Estadual do Oeste do Paraná
Cascavel |
Programa de Pós-Graduação: |
Programa de Pós-Graduação em Ciência da Computação
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Departamento: |
Centro de Ciências Exatas e Tecnológicas
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País: |
Brasil
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Palavras-chave em Português: | |
Palavras-chave em Inglês: | |
Área do conhecimento CNPq: | |
Link de acesso: | https://tede.unioeste.br/handle/tede/7089 |
Resumo: | Currently, all computers feature some level of usable parallelism. Modern systems are explicitly equipped with hardware support for this functionality, including multiple nodes, cores, CPUs, and accelerators. However, software development for parallel computers is challenging due to the variety of considerations programmers must address during the creation process. In addition to hardware-related challenges, the dynamic nature of applications, subject to unexpected load variations, is common in the context of High Performance Computing (HPC). In this regard, parallel patterns have been proposed to mitigate some complexities. Nevertheless, there is a notable absence of standards addressing the design and construction of elastic applications. Thus, this work aims to expand upon existing standards in the literature by proposing a model for application development and patterns that incorporate support for elasticity. The objective is to assist the developer in all phases of designing and implementing parallel applications. Additionally, the work encompasses a review of some frameworks that can be employed to implement elastic applications. Finally, this work demonstrates the application of this model and the proposed elastic patterns in defining the architecture of applications used in HPC. This study advances towards a programming mindset that recognizes the importance of dealing with different offerings and variations of hardware and software, a crucial aspect for the next generation of HPC applications. |