Especificação, desenvolvimento e prototipagem de um protocolo de alta disponibilidade em FPGA

• Ano de defesa: 2013
• Autor(a) principal: Oliveira, Rômerson Deiny
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Uberlândia; BR; Programa de Pós-graduação em Ciência da Computação; Ciências Exatas e da Terra; UFU
• Palavras-chave em Português: Alta disponibilidade; Cérebro partido; FPGA; HARP; Operação de rede; VRRP; Redes de computadores - Protocolos; High availability; Network operation; Split brain; CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO
• Link de acesso: https://repositorio.ufu.br/handle/123456789/12549

The increasing number of users connected to the Internet led it to become a major vehicle for personal and business transactions in the last years. Nevertheless, its unavailability can result in losses, including nancial ones, for its users. Despite of all eorts to keep the network availability nearest to 100% of the time, reasearches have shown that the existing protocols have two algorithmic problems caused by message losses or disruption, named No Brain and Split Brain, which attack the network availability and lead it to crash. Thus, those researches propose that such protocols must be changed considering the possibility of message loss. In this way, this research species and implements the High Availability Router Protocol (HARP), which is a new high availability protocol that operates in stateless environments. Furthermore, a validation system is presented to test high availability protocols for the sake of link failures. The specication concerns to environment assumptions, services, vocabulary, format and procedure rules specied by nite state machine, moreover, the specication is complemented with a TLA+ formal description regarding concurrent systems context intending to ratify the HARP good properties. The HARP implementation consists of its prototyping on FPGA and the validation system based on a System-on-Programmable Chip (SOPC).