Estimulador elétrico funcional com balanceamento ativo de cargas integrado em tecnologia CMOS de 130nm

• Ano de defesa: 2017
• Autor(a) principal: Silveira, Rafael Silveira da
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Santa Maria; Brasil; Ciência da Computação; UFSM; Programa de Pós-Graduação em Ciência da Computação; Centro de Tecnologia
• Palavras-chave em Português: Estimulação elétrica funcional; Neuroestimulador; Balanceamento de carga; Functional electrical stimulation; Neurostimulation; Charge balancing; CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO
• Link de acesso: http://repositorio.ufsm.br/handle/1/14664

Functional electrical stimulation (FES) is a technique that has been used to restore neurological functions. Successful examples of the use of FES include hearing and vision recoveries in patients suffering from neurological disorders. However, one of the main concerns with regard to neurostimulation is to ensure a safe operation, ie, to not cause any damage to the tissue as a result of long-term electrical stimulation. The accumulation of charges in the tissue can lead to corrosion of the electrode and the generation of toxic material that damages the tissue. Aiming this safety, a methodology is proposed for the control of charge unbalance through a feedback circuit and the alternation of electric pulses. The current work objective is to propose the implementation of a Neurostimulator with active charge balancing in 130 nm CMOS technology. An essential decision that needs to be made in a Neurostimulator project is the choice of manufacturing technology. Considering the choice of a low voltage 130nm technology, a voltage tolerant switch implementation methodology is also proposed, which aims to share the same baseline of the digital circuits, reducing costs and also the area of the circuit itself. All results are demonstrated at the schematic simulation level, including the parameters extracted from the layout and Monte Carlo analysis to validate the circuit. The project was fabricated through the "MPW" (multi-program wafer) program of the IMEC, but the samples were not received in time to allow inclusion of test results in this work.