Compartilhamento do módulo DVS para redução de área no pixel
Ano de defesa: | 2019 |
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Autor(a) principal: | |
Orientador(a): | |
Banca de defesa: | |
Tipo de documento: | Dissertação |
Tipo de acesso: | Acesso aberto |
Idioma: | por |
Instituição de defesa: |
Universidade Federal do Rio de Janeiro
Brasil Instituto Alberto Luiz Coimbra de Pós-Graduação e Pesquisa de Engenharia Programa de Pós-Graduação em Engenharia Elétrica UFRJ |
Programa de Pós-Graduação: |
Não Informado pela instituição
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Departamento: |
Não Informado pela instituição
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País: |
Não Informado pela instituição
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Palavras-chave em Português: | |
Link de acesso: | http://hdl.handle.net/11422/12292 |
Resumo: | This work presents a study about biomorphic image sensors, with an emphasis on asynchronous time-based image sensors. In these sensors, every pixel detects its own incoming light variations. If such variations exceed pre-established reference values, then a light intensity sample must be taken. To control the asynchronous operation mode, arbiters allow pixel access to shared communication buses in an orderly fashion. Besides, the arbiters enable biomorphic pixels to independently acquire incident light samples, without a need for external control signals. Imager data readout is based on voltage spike sequences (each voltage spike is referred to as an “event”), thus leading to high-speed unquantized data transmission. We propose sharing, among pixels within a 2 × 2 or 4 × 4 pixel block, the same circuit for light intensity variation detection, in order to reduce overall device count and, as a consequence, to reduce pixel area. This modification does impair image quality, but numerical simulation results indicate that the quality loss is modest for variation detection circuit sharing with 2×2 pixel blocks. We present systemlevel simulation results obtained for a numerical description of the entire imager. These results illustrate the relationship between pixel-block size, for pixels sharing detection circuits, and the reconstructed image/video quality. We also show electrical simulations at the schematic diagram level, and assess transistor bias effects on overall imager behavior. |