Escalonamento dinâmico em nível aplicativo sensível à arquitetura e às dependências de dados entre as tarefas.

• Ano de defesa: 2014
• Autor(a) principal: Favaretto, Rodolfo Migon
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Pelotas; Centro de Desenvolvimento Tecnológico; Programa de Pós-Graduação em Computação; UFPel; Brasil
• Palavras-chave em Português: Escalonamento em nível aplicativo; Arquiteturas NUMA; Escalonamento de tarefas paralelas; Escalonamento de listas; Application level scheduling; NUMA architectures; Parallel Task Scheduling; List Scheduling; CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO
• Link de acesso: http://guaiaca.ufpel.edu.br/handle/prefix/8596

Modern architectures have multiple processors, each of which contains multiple cores, connected to dedicated memory blocks, featuring NUMA (Non-Uniform Memory Access) architectures. NUMA have different latencies in accessing different blocks of distributed memory. A major challenge is to develop an efficient scheduling to the tasks produced by parallel applications among the available processors by considering the heterogeneity of these memory access times. For this, the scheduler must make decisions influenced by several factors. One of these factors is related to issues of data locality, the decision of allocate a task on a specific processor is an assessment of the costs associated to the access to its data on the asymmetric memory structure. Another factor to be considered is related to the data dependences used by tasks, where heuristics based on list algorithms can be used to scheduling these tasks, in application level, in dynamic execution environments. In this work, we designed a dynamic scheduling strategy for parallel applications on NUMA architectures. This strategy was validated by a series of experiments, where it was possible to assess its performance by comparing it against other tools that employ scheduling on application level. The aim of the strategy was reduced the impact, when executing parallel aplications, of the different latencies arising from the physical distribution of memory modules in NUMA architectures. This work resulted in an extension of the Anahy execution core, which now comprise the proposed strategy, considering, at the time of scheduling, the heterogeneous characteristics of the architecture where the application is running. The results show that the proposed strategy improved the quality of Anahy scheduling on NUMA architectures, contributing to the increased performance of this environment. Compared to other tools, the proposed strategy proved compatible.