Otimização genética de sequências de padrões de teste para circuitos VLSI.

• Ano de defesa: 2016
• Autor(a) principal: Dias, Leonardo Alves
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal da Paraíba; Brasil; Engenharia Elétrica; Programa de Pós-Graduação em Engenharia Elétrica; UFPB
• Palavras-chave em Português: Teste de circuitos integrados, geradores de padrões de teste, consumo energético, algoritmo de Berlekamo-Massey.; Integrated circuit pattern , test pattern generators , energy consumption , Berlekamo -Massey algorithm.; ENGENHARIAS::ENGENHARIA ELETRICA
• Link de acesso: https://repositorio.ufpb.br/jspui/handle/tede/8501

An integrated circuit (IC) in test mode has a higher energy consumption compared to the normal operating mode, due to the increased number of transitions in the nodes of the resulting circuit applying test patterns used to stimulate the CI during the test run resulting in high power dissipation which can damage the IC, resulting in higher costs for manufacturers. In this work we propose a genetic algorithm to optimize sequences of test patterns aiming at low energy consumption during the test run, maintaining an adequate fault coverage. It is also proposed using the Berlekamp-Massey algorithm to synthesize an integrated test patterns with low hardware sobreárea generator capable of generating sequences optimized based on Shift Register with Linear Feedback. The optimization of the sequences is done by reducing the number of transitions at nodes whose evaluation is done by a computer program developed in this study in C ++. Finally, simulations were performed with the genetic algorithm to check the behavior to optimize the number of transitions, the fault coverage and hardware sobreárea.