Digital design of a forward error correction system for IEEE 802.15.7

• Ano de defesa: 2020
• Autor(a) principal: Mateus Gonçalves Silva
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: eng
• Instituição de defesa: Universidade Federal de Minas Gerais; Brasil; ENG - DEPARTAMENTO DE ENGENHARIA ELÉTRICA; Programa de Pós-Graduação em Engenharia Elétrica; UFMG
• Palavras-chave em Português: Sistemas digitais; Código de correção de erro; IEEE 802.15.7; Propriedade intelectual; Comunicação por luz visível; Engenharia elétrica
• Link de acesso: http://hdl.handle.net/1843/35091

Visible Light Communication (VLC) is an emerging field that has attracted attention in recent times, and it has been proposed as a complement or even an alternative to the conventional RF systems. The motivation for it is that the latter is suffering from a phenomenon known as RF spectrum crunch - due to the overuse of wireless communication in user-end applications. The first global attempt to standardize VLC was promoted by IEEE 802.15.7, which specifies the Physical (PHY) and Media Access Control (MAC) layers for short range VLC. It has three PHY layers (I, II, and III) with thirty operating modes suitable for a wide range of noisy channel conditions. The main element of them is the Forward Error Correction (FEC) component, which defines a set of error control techniques Reed Solomon (RS) codes, Interleaving, and Convolutional Codes (CC) employed to improve the capacity of the transmission channel. The goal of this master thesis is to propose a digital system that implements a FEC compliant with IEEE 802.15.7. The main outcome of this work is an open access Intellectual Property (IP) Core for the FEC, followed by a comprehensive explanation of its related Register Transfer Level (RTL) architecture. Most attempts for implementing a IEEE 802.15.7 compliant system is targeted to prototype applications in embedded platforms, whereas dedicated digital devices are more appropriate for the hardware realization of PHY layers. Moreover, the availability of reliable IP Cores for communication such as the FEC and its base blocks is scarce. These facts corroborate the demand for the intended work. Verification and synthesis of the resulting IP Core are carried out by both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) flows, and their results for size, timing and power consumption are analyzed and cross validated. IEEE 802.15.7 requirements for throughput and latency are also checked for the FEC IP Core, and they are fulfilled for most operating modes at the target device technologies. Improvements for the digital design architecture and methodology of the FEC IP Core are discussed at the end of this thesis, enabling opportunities for future academic and development projects.