Utilizando SNMP para asserções em hardware

• Ano de defesa: 2005
• Autor(a) principal: Fabricio Orlando Damasceno
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Minas Gerais; UFMG
• Palavras-chave em Português: Asserções; Hardware; Microprocessadores Projeto e construção; Circuitos integrados; Computação; Redes de computação Administração; Redes de computação Protocolos
• Link de acesso: http://hdl.handle.net/1843/SLBS-6GVF6Y

Due to the exponential increase of circuit complexity and due to the wide use of conventional veri¯cation techniques, the development of error-free circuits seems to be a di±culttask to accomplish. As the generation of project error-free circuits is not possible, a new approach must be used, allowing error detecting after the sales phase. This scenario requirescircuit monitoring in a continuous fashion, performing error detection during runtime, since error veri¯cation during simulation may not detect errors. The accomplishment of the runtime circuit monitoring process requires extra assertion logic for the entire circuits,performing a runtime check on the circuit expected behavior to detect possible inconsisten-cies. To propagate the data generated by the assertion through the circuit, a centralized process is required, named assertion processor, used to classify the assertions. This tease provides an innovative solution that uses a network to allow the visibility of the data generated by the assertion processor outside the circuit, allowing the problem solve. TheSNMP trap message has been chosen to propagate the necessary assertion data, since thismechanism has been widely used by network management systems.