Aumento de vida útil de circuitos integrados digitais com técnicas de detecção e correção de erros temporais in situ

• Ano de defesa: 2018
• Autor(a) principal: Andrei dos Santos Silva
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Minas Gerais; UFMG
• Palavras-chave em Português: Conabilidade; Vida útil; Erros temporais; Circuitos integrados digitais; Confiabilidade (Engenharia); Engenharia elétrica
• Link de acesso: http://hdl.handle.net/1843/BUOS-B8VFRA

Advances in the manufacturing processes of microelectronics devices led to an increase miniaturization of the Field Eect Transistors (FETs), reaching nanometer scale nowadays. The reduced size of such elements brought signicant increase to performance and functionality integration of computational systems. As these advances reach the submicron region, however, microelectronic devices begin to experience reliability issues during operation. Electromagnetic noise, fabrication process variations and aging eects have being identied as the main agents of integrated circuits increase susceptibility to physical failure. Many works in the literature focus in the reliability increase through the insertion of special sequential elements capable of in situ error detection and correction. These works, however, present techniques that require processing stall or clock frequency control in order to recover from such errors. The current work presents two techniques of error detection and correction for complex sequential circuits that do not require machine stalling to operate. The rst one is called Selective Time-Borrowing (EST). This technique operates through relocation of time between less constrained sequential stages in order to increase time margins for critical paths. The second one is directed to cases where no time margin is available for relocation, called Alternative Path Activation (APA). The APA uses parallel processing to recover from error without resorting to time-borrowing from other sequential stages. Both these techniques are directed at increasing digital integrated circuits reliability by targeting primarily aging eects. An automatic insertion ow to these techniques is proposed to be used on integrated circuits design. In order to validate the proposed techniques, transistor and logic level simulations were conducted with test circuits and ISPD12 benchmarks. The logic level simulations focus on insertion of the techniques on more complex circuits, assessing coverage and time margin gain. An ARMv2 processor was modied manufactured in 130nm technology in order to test both techniques in a real circuit. The proposed techniques oer the possibility to increase integrated circuits lifetime and reliability in the age of ubiquitous computing