Verificação de equivalência de circuitos com aceleração por largura e aprendizado de cláusulas de conflito

• Ano de defesa: 2007
• Autor(a) principal: Thiago Radicchi Roque
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Minas Gerais; UFMG
• Palavras-chave em Português: circuitos eletronicos; Eletrônica digital Testes; Computação; Circuitos integrados Verificação; Circuitos eletrônicos Verificação
• Link de acesso: http://hdl.handle.net/1843/RVMR-7AAPAR

Equivalence checking (EQ) is a very common formal verification method used in the semiconductor industry. It makes possible to verify if two different implementation of the same design have the same functional behavior which is very useful to make sure that the design still behaves correctly after optimizations (likeretiming) or synthesis. Several known methods are used efficiently, involving techniques like BDDs and SAT. However, the increasing complexity of digital designs turns EQ into a harder problem, motivating the research for new alternatives in this field. This work proposes a equivalence checking tool, based on the following points: design partitioning by width, a parallel SAT solver, and SAT conflict clause learning by applying induction when unrolling sequential circuits. We aim to solve bigger problems faster than the existing solutions in some cases.