Análise de cobertura e geração de vetores de teste para módulos descritos em Systemc

• Ano de defesa: 2008
• Autor(a) principal: Alair Dias Junior
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Minas Gerais; UFMG
• Palavras-chave em Português: Verificação; Cobertura de código; SoC; SystemC; Engenharia elétrica
• Link de acesso: http://hdl.handle.net/1843/BUOS-8C8HVK

The growing complexity of VLSI systems and the necessity to reduce the development time push the design cycle to its limits. Assuring the correct behavior of these designs is a major problem as the number of states to verify explodes. Today, verification is the most consuming step of SoC development, representing 70% of the total development effort. It is clear the need for new tools and methodologies to increase verification efficiency. High level design, which was first meant to reduce theproductivity gap, contributes to verification, allowing it to begin earlier in the design cycle. Although, using high-level languages to describe hardware requires a reformulation on the microelectronics industry. The natural way is to use tools and techniques developed in thesoftware industry, where these languages have been used for decades.This work has three goals. The first is to create a tool capable of analyzing the structural coverage achieved by the test vectors applied to a system described using SystemC. The tool should allow verifying the quality of the test vectors, providing information that could be used by the test engineer to improve the verification environment. The second goal is to present a method for the generation of test vectors for combinationalsystems described using SystemC. This method is expected to increase the controllability of the system, allowing the test engineer to create test vectors to exercise a given fragment of the source-code.The third goal is to describe a hibrid methodology for the test of designs described using SystemC that combines functional testing with structural testing in order to improve test performance. Using the coverage information extracted by the structural coverage tool, it is possible to determine which portions of the source-code were not exercisedproperly by the funcional test. A method for generating test vectors could be applied to create the vectors necessary to exercise these uncovered portions.