Estudo e desenvolvimento arquitetural para implementação de um classificador geométrico de margem larga em sistemas embarcados

• Ano de defesa: 2018
• Autor(a) principal: Liliane dos Reis Gade
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal de Minas Gerais; UFMG
• Palavras-chave em Português: Engenharia elétrica; Matrizes de portas programáveis no campo; Microcontroladores ARM
• Link de acesso: http://hdl.handle.net/1843/BUOS-B33K97

The present work is aimed at the study of new ways of implementing the decision rule of a large margin classier aiming at of reducing the complexity of the operations during the classication step of the new patterns, making it easier the use of this classier in embedded systems. An architecture in data ows of the geometric classier was also developed, taking full advantage of the intrinsic parallelism of Field Programmable Gate Arrays (FPGAs). This architecture was tested and simulated on real data sets commonly used in the literature. The results showed a high performance and consumption of resources obtained by the architecture. The consumption of resources increase exponentially with the number of training samples, thus making it not very adequate in systems with large training samples. Because of that, a 32-bits ARM microcontroller implementation was performed and the tests were repeated and compared with the previous architecture. The results showed that the running time of the algorithm in microcontroller is larger than in FPGAs, since it does not have the characteristics of parallelism. However the resource consumption is smaller, in systems that have a higher number of training samples