O efeito da largura de Fetch no desempenho das arquiteturas super escalar, trace cache e DTSVLIW

• Ano de defesa: 2003
• Autor(a) principal: Freitas, Christian Daros de
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal do Espírito Santo; BR; Mestrado em Informática; Centro Tecnológico; UFES; Programa de Pós-Graduação em Informática
• Palavras-chave em Português: Arquitetura de computador; Memória cache; Ciência da Computação; 004
• Link de acesso: http://repositorio.ufes.br/handle/10/6349

Superscalar machines fetch multiple scalar instructions per cycle from the instruction cache. However, machines that fetch no more than one instruction per cycle from the instruction cache, such as Dynamically Trace Scheduled VLIW (DTSVLIW) machines, have shown performance comparable to that of Superscalars. In this paper we present experiments which show that fetching a single instruction from the instruction cache per cycle allows the same performance achieved fetching multiple instructions per cycle thanks to the execution locality present in programs. We also present the first direct comparison between the Superscalars, Trace Cache and DTSVLIW architectures. Our results show that a DTSVLIW machine capable of executing up to 16 instructions per cycle can perform 21.9% better than a Superscalar and 6.6% better than a Trace Cache with equivalent hardware. In the comparison between a DTSVLIW machine and an Alpha 21264 machine, we have shown that the DTSVLIW can perform 24,17% better than Alpha using integer programs, and 60,36% better than Alpha using floating point programs.