Geração de código otimizado visando a exploração de paralelismo na arquitetura IPNoSys

• Ano de defesa: 2016
• Autor(a) principal: Couto, Juliene Vieira do
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Universidade Federal Rural do Semi-Árido; Brasil; UFERSA; Programa de Pós-Graduação em Ciência da Computação
• Palavras-chave em Português: Arquiteturas paralelas; Compilador; IPNoSys; Otimização; Nível de otimização; Parallel archtectures; Compiler; Optimization; Levels of Optimization; CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO
• Link de acesso: https://repositorio.ufersa.edu.br/handle/tede/652

Parallel architectures require optimized code that exploits its new features. Some architectures follow the paradigm of Von Neumann machine, while others differ from this model, such as IPNoSys processor. This processor is based on network-on-chip and features a package-driven computer model driven which reflects in its programming model. Initially, this architecture had an assembler and a simulator and needed a compiler. In later papers compilers for IPNoSys have been developed, but none fully explored the features of this architecture. Thus, the objective of this paper is to define a code optimization step in IPNoSys compiler, considering characteristics unexploited as parallelism and improving your generated code. The optimization module offers three levels of optimization. In order to evaluate the created module, made a comparison of the execution time and the size of codes generated in the three levels of optimization. It was obtained that an optimization level showed better run time, but generated applications with a larger size, while another level showed a smaller size. Furthermore, there was an improvement in the generated code