MPSoC tolerante a falhas para coprocessamento compartilhado de extensão do ISA RISC através de NoCs

• Ano de defesa: 2020
• Autor(a) principal: Lima, Pedro Lucas Falcão
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Palavras-chave em Português: RISC-V; ISA; Extensão; Recursos Compartilhados; MPSoC; NoC; Tolerância a falhas
• Link de acesso: http://www.repositorio.ufc.br/handle/riufc/58128

The increased integration of devices has enabled the construction of SoC type architectures composed of several processors, allowing to meet the growing demand for functionality required by emerging embedded applications. Among these architectures is the MPSoC , which is composed of a set of processors containing an ISA with some instructions of high cost of implementation and rarely used, causing loss of performance and underutilization of the MPSoC. This work proposes an MPSoC that makes possible to extend the basic ISA of the RISC-V architecture through shared resources among processors. The strategy used consists in executing instructions in specialized modules distributed in the system when there is no support in the processor datapath. In addition, a fault-tolerant architecture was developed for the unavailability of coprocessors in several error positions and number of error loads. To evaluate the methodology used, several systems were implemented that were evaluated regarding area consumption, power dissipation, maximum operating frequency and number of cycles for the total execution of applications. After that, an expanded system was implemented, capable of receiving failures in several ways. The evaluation of the expanded system was done in several metrics (number of cycles, number of instructions instructions and in synthesis data). The experimental results allowed us to conclude that the proposed technique of resource sharing allowed us to reduce the execution time of the analyzed applications at a low hardware cost. Besides, it showed the viability of NoC expansion and the use of fault tolerance in this developed architecture