OPENOBC: uma arquitetura de um computador de bordo open source e de baixo custo para o padrão CUBESAT

• Ano de defesa: 2017
• Autor(a) principal: Mota, David Freitas Moura
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Palavras-chave em Português: Teleinformática; Hardware; Arquitetura de computador
• Link de acesso: http://www.repositorio.ufc.br/handle/riufc/22986

The definition of the CubeSat standard boosted the research and development of the pico and nano satellites inside of the universities. Besides the standardization of the physical dimensions, the CubeSat specifies a communication protocol between the sub-systems of the satellite, what can make possible the shortening of the time and cost of the project using COTS (Comercial off-the-shelf) components. Although cost is an important requirement for the development of small satellites, the cost reduction must come from the correct architecture choice, not from the loss of system reliability. Focusing in a specific component, like the OBC (On Board Computer), becomes clear that the currents solutions meets the low cost requirements but fails in providing high failure tolerance. Some OBC models do not provide a mechanism of detection and correction of failures, while others cover only partially the failure points with a way to correct errors in external memories. At this job will be proposed an open source architecture with low cost and high reliability for an on board computer with compatibility with the CubeSat standard. The proposal architecture uses a TMS570LS0432 processor from Texas Instruments, which have dual ARM Cortex-R4 core, detection and failure correction in RAM and internal ROM, hardware BIST (built-in self test) at the CPU and RAM memory and others securities characters like clock monitoring and power supply voltage. An external flash memory was used for storage of code and data. Two I2C interfaces for communication between the sub systems, one had been used exclusively for transponder communication and the other one for the other systems. The architecture is complemented with an UART interface for diagnosis and debugging, PWM signals for activate the torque coils and ADC inputs for light measuring in the satellite. A MicroSD card reader has been planned for data storage and a CAN bus for data traffic in real time, ensuring a rigid control of failures and messages receiving. The OBC was electronically tested and is able to be embedded with the others sub systems.