Um código extensível para correção de multiple bit upsets em memórias

• Ano de defesa: 2018
• Autor(a) principal: Silva, Felipe Gaspar Alan e
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Palavras-chave em Português: Teleinformática; Tolerância a falha (Computadores); Códigos corretores de erros (Teoria da informação); Circuitos integrados - Memória
• Link de acesso: http://www.repositorio.ufc.br/handle/riufc/34699

The scaling down of electronic devices along with the processing increase, has made them more sensitive to the effects of radiation coming mainly from space. Memories are circuits highly susceptible to these effects, having great possibility of presenting errors in multiple bits(MBU), which can cause critical failures in the system. Error Correcting Codes(ECCs) are widely applied to deal with the occurrence of such errors. However, the application of an ECC with large corrective capacity can lead to increased area, power and delay cost, causing loss of performance. The CLC code is na ECC that uses concepts of Extended Hamming and parity code, forming a matrix capable of handling MBU in memories, though presenting low implementation cost when compared to more robust codes. Despite this, the code has weaknesses compered to its competitors. One is the number of redundancy bits generated, which for a 16-bit word of data, requires 150% more bits of the original word. The CLC code did not presented good capability to correct very aggressive MBU patterns (6, 7 and 8 errors), that with the increasing miniaturization of integrated circuits, the probability of these types of errors occurring became a real concern in environments with large radiation incidence. This work proposes to treat the problems mentioned through changes in the matrix of the CLC code, by the modification of the Extended Hamming applied. In addition, we evaluated the scalability of the code for larger data bits words. The proposed Extended Hamming modification brought two new structures for the CLC code, one that has less redundancy bit addition and lower implementation cost, and another that has bigger error detection and correction capabilities. The scalability analysis shows that for larger data words, the bit rate generated by the CLC decreases, mainly for one of the proposed structure, falling from 143,75 % for 16-bit data, to 82,81% for 64-bit data. Finally, this work also performed tests of reliability and synthesis, in which the development of the new structures for the CLC presented substantial improvements, bringing bigger flexibility of application for this code.