Reduction of energy consumption in MPSOCS through a dynamic frequency scaling technique

• Ano de defesa: 2012
• Autor(a) principal: Rosa, Thiago Raupp da
• Orientador(a): Moraes, Fernando Gehm
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Pontifícia Universidade Católica do Rio Grande do Sul
• Programa de Pós-Graduação: Programa de Pós-Graduação em Ciência da Computação
• Departamento: Faculdade de Informáca
• País: BR
• Palavras-chave em Português: INFORMÁTICA; MULTIPROCESSADORES; ARQUITETURA DE COMPUTADOR
• Área do conhecimento CNPq: CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO
• Link de acesso: http://tede2.pucrs.br/tede2/handle/tede/5180

NoC-based MPSoCs are employed in several embedded systems due to the high performance, achieved by using multiple processing elements (PEs). However, power and energy restrictions, especially in mobile applications, may render the design of MPSoCs over-constrained. Thus, the use of power management techniques is mandatory. Moreover, due to the high variability present in application workloads executed by these devices, this management must be performed dynamically. The use of traditional dynamic voltage and frequency scaling (DVFS) techniques proved to be useful in several scenarios to save energy. Nonetheless, due to technology scaling that limits the voltage variation and to the slow response of DVFS schemes, the use of such technique may become inadequate in newer DSM technology nodes. As alternative, the use of dynamic frequency scaling (DFS) may provide a good trade-off between power savings and power overhead. This work proposes a self-adaptable distributed DFS scheme for NoC-Based MPSoCs. Both NoC and PEs have an individual frequency control scheme. The DFS scheme for PEs takes into account the PE computation and communication loads to dynamically change the operating frequency. In the NoC, a DFS controller uses packet information and router activity to decide the router operating frequency. Also, the clock generation module is designed to provide a clock signal to PEs and NoC routers. The clock generation method is simple, based on local selective clock gating of a single global clock, provides a wide range of generated clocks, induces low area and power overheads and presents small response time. Synthetic and real applications were used to evaluate the proposed scheme. Results show that the number of executed instructions can be reduced by 65% (28% in average), with an execution time overhead up to only 14% (9% in average). The consequent power dissipation reduction in PEs reaches up to 52% (23% in average) and in the NoC up to 76% (71% in average). The power overhead induced by the proposed scheme is around 3% in PEs and around 10% in the NoC