Desenvolvimento de uma metodologia de injeção de falhas de atraso baseada em FPGA

• Ano de defesa: 2013
• Autor(a) principal: Marroni, Nícolas
• Orientador(a): Poehls, Leticia Maria Bolzani
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Pontifícia Universidade Católica do Rio Grande do Sul
• Programa de Pós-Graduação: Programa de Pós-Graduação em Engenharia Elétrica
• Departamento: Faculdade de Engenharia
• País: BR
• Palavras-chave em Português: ENGENHARIA ELÉTRICA; ENGENHARIA ELETRÔNICA; CIRCUITOS ELETRÔNICOS; INJEÇÃO ELETRÔNICA; FALHA DE SISTEMA (ENGENHARIA)
• Área do conhecimento CNPq: CNPQ::ENGENHARIAS::ENGENHARIA ELETRICA
• Link de acesso: http://tede2.pucrs.br/tede2/handle/tede/3057

With the evolution of CMOS technology, density and proximity between routing lines of integrated circuits (ICs) have increased substantially in the recent years. Slight variations in the manufacturing process, as the undesired connection between adjacent tracks and variations in threshold voltage due to changes in the lithographic process can cause the IC to behave anomalously. In this context, the development of new test methodologies, which are capable of providing high capacity fault detection in order to identify defects, becomes essential. Specifically when manufacturing ICs using technologies below 65nm, the use of test methodologies that aim at detecting delay faults is crucial, thus the production process does not cause a change in the resulting logic circuit's behaviour, but only a change in the circuit's timing. Thereby, this master thesis proposes the development of a methodology for the injection of delay faults in order to extract the delay fault coverage and to analyse the efficiency of existing methodologies for complex ICs. The proposed approach aims at guiding the insertion of delay faults into specific points of the IC. Such insertion points are results of the probabilistic variation in the manufacturing process of large-scale integrated circuits and can be used in modelling delay faults arising from such variations. Through the specification, implementation, validation and assessment of an emulation tool in the Field-Programmable Gate Array (FPGA) it will be possible to understand the degree of robustness of complex integrated systems against delay faults, extract the fault coverage and evaluate the efficiency of both test methodologies and techniques for fault tolerance.