Avaliação sistemática de redes intrachip

• Ano de defesa: 2014
• Autor(a) principal: Schneider, William
• Orientador(a): Calazans, Ney Laert Vilar
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Pontifícia Universidade Católica do Rio Grande do Sul
• Programa de Pós-Graduação: Programa de Pós-Graduação em Ciência da Computação
• Departamento: Escola Politécnica
• País: Brasil
• Palavras-chave em Português: Redes Intrachip; Sistemas Integrados em Chip; Avaliação de Desempenho
• Palavras-chave em Inglês: NoC (Networkon Chip); Benchmarking; Intrachip Networks; SoC (Systems on a Chip); Performance Evaluation
• Área do conhecimento CNPq: CIENCIA DA COMPUTACAO::TEORIA DA COMPUTACAO
• Link de acesso: http://tede2.pucrs.br/tede2/handle/tede/8202

The increase in the number of cores available in Systems on a Chip has enabled the design of circuits with increasingly aggressive specifications. Efficient interconnection architectures such as intrachip networks are critical to the viability of these projects. However, measuring and comparing performanceof these networks for a given system is still a challenging task, which results from: (i) the complexity imposed by the abundance of available options in the design space of these networks; (ii) the current non-adoption of a unique evaluation platform to compare different networks proposals; (iii) the fact that the network traffic has a greater influence on the performance of such networks than any other design characteristic. This work has as main strategic goal the evaluation and comparison of different intrachip network architectures through the use of a unified evaluation platform. It adopts Nocbench, a recent platform, already validated in some contexts and proposed as a standard for the evaluation of intrachip networks. The employed evaluation method is based on the simulation of networks and uses as input traffic and computation models described in the form of traces, both extracted from real application. The main contributions of this work reside in: (i) the proposal of several enhancements to the chosen platform; (ii) the development of modules added to integrate the networks Hermes HS,Hermes OO, Hermes TB, Hermes VC, and YeaH from the author´s research group to the platform; (iii) the enhancement of the platform performance evaluation process, through the inclusion of metrics usually employed to compare intrachip networks, including: latency, throughput and jitter. A set of experiments validates the contributions and demonstrate the use the Nocbench platform as a useful tool in the comparison of intrachip networks of diverse origins.