Estudo e desenvolvimento em hardware de códigos corretores de erros

• Ano de defesa: 2007
• Autor(a) principal: Cargnini, Luís Vitório
• Orientador(a): Fagundes, Rubem Ribeiro
• Tipo de documento: Dissertação
• Tipo de acesso: Acesso aberto
• Idioma: por
• Instituição de defesa: Pontifícia Universidade Católica do Rio Grande do Sul; Porto Alegre
• Palavras-chave em Português: ENGENHARIA ELÉTRICA; INFORMÁTICA; FPGA; CIRCUITOS INTEGRADOS - INTEGRAÇÃO EM ESCALA MUITO AMPLA
• Link de acesso: http://hdl.handle.net/10923/3197

This work has been developed error correcting codes: the Bose-Chaudhuri- Hocquenghem (BCH) and the Reed-Solomon (RS). Coders BCH had been implemented directly from the algebraic approach, using as tool, a hardware description language (VHDL), as well as the implementation of prototypes using Field Programable Gate Arrays (FPGA). The achieved results had clearly showed that the increasing performance of these code algorithms, either in the aspect of execution speed, and in FPGA device area usage. The achieved success in the code implementation in FPGA was not about the implementation itself, since there are some similar accomplishments in the market and the academy. The main stone is the fact of using the original algebraic formulation, that is, without the job of usual iterative algorithms (sequential) in the implementation of the BCH. With the results of the BCH algebraic a new code for symbols based in the BCH, has been proprosed, that will be presented as a new alternative to the Reed-Solomon, for surpassing it, as much in time as area to be implemented. Thus, this work test that, with the advance of the resources for rapid prototyping of Very Large Scale Integration (VLSI) technologies, and the hardware description of the code using it original algebraic description, results in a system with impressive performance, as consequence of the paradigm changing, based until the moment in polynomial sequential processing, to a new paradigm of hardware parallelism, executing the algebraic model.