Vericação funcional de sistemas digitais utilizando algoritmos genéticos na geração de dados aplicada a metodologia veriSC
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| Main Author: | |
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| Publication Date: | 2014 |
| Format: | Master thesis |
| Language: | por |
| Source: | Repositório Institucional da UFG |
| Download full: | http://repositorio.bc.ufg.br/tede/handle/tede/5028 |
Summary: | The process of creating an Intellectual Property Core (IP-core) has become more complex with the advent of electronic circuit technology, encouraging the development of new techniques and methodologies to assist this process. A fundamental and critical stage of a hardware design is the hardware verification phase. At this phase it is verified that the IP-core was implemented according to their specification, ensuring that it is feasible to prototyping and their large-scale production (System on Chip). The verification phase corresponds to the biggest bottleneck in a hardware design (BERGERON,2006). The VeriSC methodology is an implemented methodology to perform the hardware verifi- cation through simulation, that is, by means of functional verification. This work aims to complement the VeriSC methodology through the development of an algorithm based on the concept of Genetic Algorithms (GAs). The proposed algorithm will modify the data generation of this methodology, whose objective is to reduce the verification time and to improve the generated data by changing the data from pseudorandom mode to random-guided mode, increasing the reliability of the verification performed by the VeriSC methodology. The algorithm has a generic part (templates) that helps the implementation of new environment for the functional verification of new DUVs and it can be incorpo- rated into other functional verification methodologies. Finally, are presented three case studies, the stimuli created using GA are compared with the old implementation of VeriSC methodology. |
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