A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding

Detalhes bibliográficos
Autor(a) principal: Nalluri, Purnachand
Data de Publicação: 2016
Idioma: eng
Título da fonte: Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
Texto Completo: http://hdl.handle.net/10773/15442
Resumo: Video coding has been used in applications like video surveillance, video conferencing, video streaming, video broadcasting and video storage. In a typical video coding standard, many algorithms are combined to compress a video. However, one of those algorithms, the motion estimation is the most complex task. Hence, it is necessary to implement this task in real time by using appropriate VLSI architectures. This thesis proposes a new fast motion estimation algorithm and its implementation in real time. The results show that the proposed algorithm and its motion estimation hardware architecture out performs the state of the art. The proposed architecture operates at a maximum operating frequency of 241.6 MHz and is able to process 1080p@60Hz with all possible variables block sizes specified in HEVC standard as well as with motion vector search range of up to ±64 pixels.
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spelling A fast motion estimation algorithm and its VLSI architecture for high efficiency video codingEngenharia electrotécnicaVídeo digitalCodificação de imagemCompressão de imagemMovimento - EstimaçãoAlgoritmosArquitectura de computadoresFPGA (Field programmable gate arrays)Video coding has been used in applications like video surveillance, video conferencing, video streaming, video broadcasting and video storage. In a typical video coding standard, many algorithms are combined to compress a video. However, one of those algorithms, the motion estimation is the most complex task. Hence, it is necessary to implement this task in real time by using appropriate VLSI architectures. This thesis proposes a new fast motion estimation algorithm and its implementation in real time. The results show that the proposed algorithm and its motion estimation hardware architecture out performs the state of the art. The proposed architecture operates at a maximum operating frequency of 241.6 MHz and is able to process 1080p@60Hz with all possible variables block sizes specified in HEVC standard as well as with motion vector search range of up to ±64 pixels.A codificação de vídeo tem sido usada em aplicações tais como, vídeovigilância, vídeo-conferência, video streaming e armazenamento de vídeo. Numa norma de codificação de vídeo, diversos algoritmos são combinados para comprimir o vídeo. Contudo, um desses algoritmos, a estimação de movimento é a tarefa mais complexa. Por isso, é necessário implementar esta tarefa em tempo real usando arquiteturas de hardware apropriadas. Esta tese propõe um algoritmo de estimação de movimento rápido bem como a sua implementação em tempo real. Os resultados mostram que o algoritmo e a arquitetura de hardware propostos têm melhor desempenho que os existentes. A arquitetura proposta opera a uma frequência máxima de 241.6 MHz e é capaz de processar imagens de resolução 1080p@60Hz, com todos os tamanhos de blocos especificados na norma HEVC, bem como um domínio de pesquisa de vetores de movimento até ±64 pixels.Universidade de Aveiro2016-04-13T15:48:06Z2016-01-01T00:00:00Z2016doctoral thesisinfo:eu-repo/semantics/publishedVersionapplication/pdfhttp://hdl.handle.net/10773/15442TID:101422750engNalluri, Purnachandinfo:eu-repo/semantics/openAccessreponame:Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)instname:FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologiainstacron:RCAAP2024-05-06T03:56:42Zoai:ria.ua.pt:10773/15442Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireinfo@rcaap.ptopendoar:https://opendoar.ac.uk/repository/71602025-05-28T13:52:05.633562Repositórios Científicos de Acesso Aberto de Portugal (RCAAP) - FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologiafalse
dc.title.none.fl_str_mv A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding
title A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding
spellingShingle A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding
Nalluri, Purnachand
Engenharia electrotécnica
Vídeo digital
Codificação de imagem
Compressão de imagem
Movimento - Estimação
Algoritmos
Arquitectura de computadores
FPGA (Field programmable gate arrays)
title_short A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding
title_full A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding
title_fullStr A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding
title_full_unstemmed A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding
title_sort A fast motion estimation algorithm and its VLSI architecture for high efficiency video coding
author Nalluri, Purnachand
author_facet Nalluri, Purnachand
author_role author
dc.contributor.author.fl_str_mv Nalluri, Purnachand
dc.subject.por.fl_str_mv Engenharia electrotécnica
Vídeo digital
Codificação de imagem
Compressão de imagem
Movimento - Estimação
Algoritmos
Arquitectura de computadores
FPGA (Field programmable gate arrays)
topic Engenharia electrotécnica
Vídeo digital
Codificação de imagem
Compressão de imagem
Movimento - Estimação
Algoritmos
Arquitectura de computadores
FPGA (Field programmable gate arrays)
description Video coding has been used in applications like video surveillance, video conferencing, video streaming, video broadcasting and video storage. In a typical video coding standard, many algorithms are combined to compress a video. However, one of those algorithms, the motion estimation is the most complex task. Hence, it is necessary to implement this task in real time by using appropriate VLSI architectures. This thesis proposes a new fast motion estimation algorithm and its implementation in real time. The results show that the proposed algorithm and its motion estimation hardware architecture out performs the state of the art. The proposed architecture operates at a maximum operating frequency of 241.6 MHz and is able to process 1080p@60Hz with all possible variables block sizes specified in HEVC standard as well as with motion vector search range of up to ±64 pixels.
publishDate 2016
dc.date.none.fl_str_mv 2016-04-13T15:48:06Z
2016-01-01T00:00:00Z
2016
dc.type.driver.fl_str_mv doctoral thesis
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
status_str publishedVersion
dc.identifier.uri.fl_str_mv http://hdl.handle.net/10773/15442
TID:101422750
url http://hdl.handle.net/10773/15442
identifier_str_mv TID:101422750
dc.language.iso.fl_str_mv eng
language eng
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.publisher.none.fl_str_mv Universidade de Aveiro
publisher.none.fl_str_mv Universidade de Aveiro
dc.source.none.fl_str_mv reponame:Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
instname:FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologia
instacron:RCAAP
instname_str FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologia
instacron_str RCAAP
institution RCAAP
reponame_str Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
collection Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
repository.name.fl_str_mv Repositórios Científicos de Acesso Aberto de Portugal (RCAAP) - FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologia
repository.mail.fl_str_mv info@rcaap.pt
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