Automated Flat Circuit-Level Topology Generation Circuit Synthesis using Genetic Algorithms - Gomes, Miguel Pinto Campilho (2024)
Digital and analog circuit design for integrated circuits classically has three distinct stages: topology choice, component sizing and layout generation. In the Electronic Design Au- tomation (EDA) field, the automatic topology synthesis stage is the least developed stage, particularly for analog circuits. Analog circuit design is still essentially based on human expert designers and is generally geared toward the reuse of well-known topologies in new circuit functions or to improve existing circuit topologies and, less often, to create new circuit topologies. Generation of circuit topologies can be seen as a search and optimization problem and, therefore, it can be performed with Genetic Algorithms (GAs). What is presently unclear is to what extent this can be accomplished by a GA, particularly when handled at flat circuit- level, and in concrete for the case of MOS integrated amplifiers. Boosted by the current submicron technologies used in today’s integrated circuits, MOS integrated amplifiers have high efficiencies and very optimized specifications compared to the not-so-distant past. Eventually, an automatically generated topology could not only meet such specifications, but achieve it being a novelty, that is, potentially a GA can generate new topologies different from the traditional ones. The work described in this thesis concerns the use of GAs in automatic circuit synthesis at flat circuit-level, and tries to understand its merits and its limitations, i.e., what are the capabilities of a GA in producing useful circuits and what is the relevance of additional enhancement techniques in its overall performance. In this work a GA kernel has been de- veloped using parallelism in some stages of the algorithm, namely where it is most relevant which is in the fitness evaluation stage. In this stage, fitness evaluation is accomplished by a spice-like circuit simulator run using thread-level parallelism. Part of the difficulty of obtaining good results with GAs is the choice of the codification scheme of the problem. Several coding schemes can be used for electric circuits and in this work there was a first attempt to use a codification technique for circuits that applies the classic bit strings used by the canonic (or original) GA to represent a circuit. In this representation there is a fixed number of components available to the GA and the evolution takes place by changing the nodes to which each component terminal is connected to. In several experimental results obtained with this coding simple circuits were synthesized, such as NAND gates with MOS transistors. But scaling to more complex topologies was not possible. Hence, another codification technique was attempted, and variable-length chromosomes (VLCs) were tested. Using VLCs and an encoding scheme in which a chromosome is a circuit descriptor and each gene is a component descriptor, circuits of higher complexity were synthesized by the GA, like other logic gates never successfully generated before (e.g., XOR gate and half-adder) and analog circuits (such as amplifiers of gain up to 40 dB and GBW ≈ 70 MHz ). In addition, a few techniques have been developed and incorporated in the GA which contribute to its robustness, leading to better and faster results. Robustness is enhanced because the GA has less sensitivity to initial pseudo-random generator seed and to some parameters. Better results are obtained since circuits are produced with less redundant or useless components. Also, faster results are obtained because less time is spent in circuit simulation (since the number of components in intermediate circuits is high only during a set of iterations strictly necessary). One enhancement technique presented is a heuristic that implements an adaptive proba- bility of acceptance of mutated chromosomes according to a measure of the quality of the solutions obtained. This technique enhances local exploration capabilities of the GA and reduces sensitivity to mutation probability. Another improvement technique is a “circuit cleaning” technique that eliminates redundant components in the circuit in which we dy- namically adapt the weight of a constraint to steer the algorithm towards the sub-objective of minimizing the number of components. In addition to this technique, a segmentation procedure of the GA evolution was presented, where several phases are used, each with different parametrization, which is a valuable technique to extend the steering of the GA towards sub-objectives. Circuits synthesized by the GA were shown using all the techniques described.