High Frequency, High Linearity and Low Noise Digital to Time Converter for Phase Adjustment

• Autor(a) principal: Pataco, Diogo Alexandre Pereira
• Data de Publicação: 2022
• Tipo de documento: Dissertação
• Idioma: eng
• Título da fonte: Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
• Texto Completo: http://hdl.handle.net/10362/152029
• topic: Binary to thermometer decoder; Differential nonlinearity (DNL); Digital Phase- Locked Loop (DPLL); Digital to time converter (DTC); Integral nonlinearity (INL); Low dropout reg- ulator (LDO); Domínio/Área Científica::Engenharia e Tecnologia::Nanotecnologia

Nowadays, fast communication systems have become vital for our lifestyle. As a result, the digital PLL fulfils a very important role as frequency synthesizer, demodulator or distributor of clock signals in microprocessors and similar digital circuits. Thus, the correction of the signal using a phase adjust- ment is essential for the good operation of the PLL. In this work, it is proposed a variable slope digital to time converter (DTC), as a programmable delay line, used for the correction of the phase of a digital PLL. The work is focused on the study of the performance of the circuit, through the evaluation of fundamental parameters such as RMS jitter, line- arity, resolution and delay range. Accordingly, it is employed a 4-bit topology using 130 nm MOSFET technology. The in- tended DTC takes advantage of CMOS inverters, due to their simplicity and low noise, and capacitors, for the programmable delay RC network. The DTC functioning is based on the activation of switching transistors to trigger the programmable capacitors, through a code to define the number of capacitors that introduce delay. The circuit is complemented with a simple CMOS inverter as a comparator that triggers when the threshold voltage is attained and an output buffer employed to correct the slopes of the signal. The proposed DTC proposed is a single-ended architecture that achieves 52.50 fs RMS jitter, and the resulting DNL and INL are equivalent to 0.1124 LSB and 0.09773 LSB, respectively. The 4-bit de- lay line has a resolution of 15.2 ps, an area of 0.018 mm2 and a power consumption of 62.8 μW from a 1.2 V low dropout regulator (LDO).