Automatic generation of a single-chip solution for board-level BIST of boundary scan boards

Bibliographic Details
Main Author: José M. M. Ferreira
Publication Date: 1992
Other Authors: Filipe S. Pinto, José S. Matos
Format: Book
Language: eng
Source: Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
Download full: https://repositorio-aberto.up.pt/handle/10216/84575
Summary: The automatic generation of a hierarchical self-test architecture for boards with boundary scan test (BST) is described, based on a test processor specifically designed to implement the basic operations required to control the BST infrastructure. An ATPG module generates the ROM containing the test program, allowing a single-chip self-test solution with minimal design-for-testability overhead. The same test processor may be used without internal ROM, when a single-chip solution is not desirable.
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spelling Automatic generation of a single-chip solution for board-level BIST of boundary scan boardsEngenharia electrotécnica, Engenharia electrotécnica, electrónica e informáticaElectrical engineering, Electrical engineering, Electronic engineering, Information engineeringThe automatic generation of a hierarchical self-test architecture for boards with boundary scan test (BST) is described, based on a test processor specifically designed to implement the basic operations required to control the BST infrastructure. An ATPG module generates the ROM containing the test program, allowing a single-chip self-test solution with minimal design-for-testability overhead. The same test processor may be used without internal ROM, when a single-chip solution is not desirable.19921992-01-01T00:00:00Zinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/bookapplication/pdfhttps://repositorio-aberto.up.pt/handle/10216/84575eng10.1109/EDAC.1992.205913José M. M. FerreiraFilipe S. PintoJosé S. Matosinfo:eu-repo/semantics/openAccessreponame:Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)instname:FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologiainstacron:RCAAP2025-02-27T18:23:28Zoai:repositorio-aberto.up.pt:10216/84575Portal AgregadorONGhttps://www.rcaap.pt/oai/openaireinfo@rcaap.ptopendoar:https://opendoar.ac.uk/repository/71602025-05-28T22:47:03.928179Repositórios Científicos de Acesso Aberto de Portugal (RCAAP) - FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologiafalse
dc.title.none.fl_str_mv Automatic generation of a single-chip solution for board-level BIST of boundary scan boards
title Automatic generation of a single-chip solution for board-level BIST of boundary scan boards
spellingShingle Automatic generation of a single-chip solution for board-level BIST of boundary scan boards
José M. M. Ferreira
Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
title_short Automatic generation of a single-chip solution for board-level BIST of boundary scan boards
title_full Automatic generation of a single-chip solution for board-level BIST of boundary scan boards
title_fullStr Automatic generation of a single-chip solution for board-level BIST of boundary scan boards
title_full_unstemmed Automatic generation of a single-chip solution for board-level BIST of boundary scan boards
title_sort Automatic generation of a single-chip solution for board-level BIST of boundary scan boards
author José M. M. Ferreira
author_facet José M. M. Ferreira
Filipe S. Pinto
José S. Matos
author_role author
author2 Filipe S. Pinto
José S. Matos
author2_role author
author
dc.contributor.author.fl_str_mv José M. M. Ferreira
Filipe S. Pinto
José S. Matos
dc.subject.por.fl_str_mv Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
topic Engenharia electrotécnica, Engenharia electrotécnica, electrónica e informática
Electrical engineering, Electrical engineering, Electronic engineering, Information engineering
description The automatic generation of a hierarchical self-test architecture for boards with boundary scan test (BST) is described, based on a test processor specifically designed to implement the basic operations required to control the BST infrastructure. An ATPG module generates the ROM containing the test program, allowing a single-chip self-test solution with minimal design-for-testability overhead. The same test processor may be used without internal ROM, when a single-chip solution is not desirable.
publishDate 1992
dc.date.none.fl_str_mv 1992
1992-01-01T00:00:00Z
dc.type.status.fl_str_mv info:eu-repo/semantics/publishedVersion
dc.type.driver.fl_str_mv info:eu-repo/semantics/book
format book
status_str publishedVersion
dc.identifier.uri.fl_str_mv https://repositorio-aberto.up.pt/handle/10216/84575
url https://repositorio-aberto.up.pt/handle/10216/84575
dc.language.iso.fl_str_mv eng
language eng
dc.relation.none.fl_str_mv 10.1109/EDAC.1992.205913
dc.rights.driver.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
instname:FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologia
instacron:RCAAP
instname_str FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologia
instacron_str RCAAP
institution RCAAP
reponame_str Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
collection Repositórios Científicos de Acesso Aberto de Portugal (RCAAP)
repository.name.fl_str_mv Repositórios Científicos de Acesso Aberto de Portugal (RCAAP) - FCCN, serviços digitais da FCT – Fundação para a Ciência e a Tecnologia
repository.mail.fl_str_mv info@rcaap.pt
_version_ 1833599865201885185

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