FPGA-based implementation of an ASK/FSK detector for railway signalling balises - Marques, Marcelo Rodrigo Almeida (2019)
This dissertation is inserted in the telecommunications field, specifically railway signalling telecommunications systems. This project was proposed by CAF Signalling and aims at implementing the safety function to assure the interoperability of both Automatic Train Protection Systems (ATP) systems, ERTMS and KER. Namely, distinguish Eurobalises and KER type balises. Throughout the work the detector is modelled in Simulink and converted to VHDL code. The final step of this dissertation is the implementation on the FPGA of a robust balise type detector capable of detecting the balise type under ideal and non-ideal conditions. The performance of the detector was evaluated with real and test balise signals under ideal conditions, AWGN noise and pulsing noise.